Apparatus for timing-aware pipelining optimization

February 05, 2016 // By Harkaran Singh , Sagar Patel

The EDA tools algorithms are written such that it will start working on the most timing critical paths in the respective cost groups, if any. During this process, it works on only the paths which are violating in timing and the paths with large positive slack are left unreported anywhere. There may be chances of getting improvements in design when those kinds of paths are also analyzed.

Nowadays most of or all the designs are optimized at as earliest stage as possible in SoC flow to avoid over-designing. Synthesis being the first step for Netlist generation focuses mainly to provide maximum restructuring to earn on maximum design performance for the system, while taking care of the various necessary factors like area and power.