In order to meet these challenging requirements, use of low power techniques like multiple power islands, switchable power domains, active/reverse well bias etc. have become ubiquitous. However, using these techniques, the designer has to ensure the correctness of power intent and physical implementation at digital SoC level as well.
To manage these new constraints and signoff checks, a designer has to rely on formats like CPF (Common Power Format) and UPF (Unified Power Format). These formats define the power intent of the design in terms of power connectivity, macro-models and a certain set of rules regarding power domain crossing, selective power switching and voltage domain crossing etc.