Challenges in Hierarchical Timing Closure Using Various Timing Models

August 20, 2014 // By Syed Shakir Iqbal, Prakul Bhagat, Freescale Semiconductors India Pvt. Ltd.

In this paper, we will discuss about some commonly used timing models (PTM, ETM and ILM) in hierarchical timing closure, evaluate their significance in terms of physical implementation and thus assess the selection of the most appropriate model for timing closure under various scenarios.

Timing models are commonly used to model I/O interface across hierarchical partitions in a design. With the evolving technology, the VLSI industry offers multiple flavors of timing models as per design requirements.
Freescale, Hierarchical Timing Closure