Enpirion: An engineer’s guide to the key steps to powering an FPGA design

January 11, 2017 // By John Dillon

FPGAs are fast becoming the key component of many embedded designs due to their dynamically reconfigurable fabric and parallel processing capability. These features make these semiconductors ideal for use in systems in application areas such as convolutional neural networks and machine learning, broadcast communications equipment, and advanced driver assistance systems (ADAS).  Likely to interface with a plethora of other components and sub-systems in addition to supporting devices such as transceivers, PLLs and memory, the FPGA typically needs multiple supply voltages, each with their own unique requirements in terms of voltage, current and transient response. For example, the FPGA core is likely to require in the 10s of Amps, with some designs now requiring up to 90 A at relatively low voltages, e.g. 0.95 VDC, while memory, interfaces and legacy logic will have requirements in the range 1.5 to 3.3 VDC. Considerations such as noise immunity are also important in the design of the power supply. Transceivers, and PLLs in particular, need to have extremely clear power rails in order to prevent jitter entering the system.

 


Figure 1 – An example early power estimator (EPE) for an FPGA-based design (Source Enpirion)

Faced with powering a new FPGA or SoC design, the engineer is advised to compile a list of all the required voltage rails together with other key critical parameters such as peak current. Another key aspect of any complex design is the need to group or sequence the power on and power down of the individual power rails. This ‘tree’ list illustrated in Figure 1 above shows an example of all the power requirements. Attention should be paid not only to the various output voltages, but also to the incoming supply. Presenting all these criteria together allows the power engineer to start architecting the power supply design.

In today’s space constrained applications, a designer must assess the physical space available and determine whether there is enough to accommodate the full mechanical design. For example, an engineer may need to add fans for forced air cooling, an element that has a major impact on the conversion efficiency of the overall power supply. The power engineer also must evaluate the area available for a high power supply and determine if it is physically possible to incorporate a discrete power design, or whether to opt for a compact space-optimised power regulator module. Discrete designs have long been seen as a potentially lower cost option, but power modules are increasingly seen as a much better cost, space, and performance alternative. However, accommodating the space required by a discrete circuit needed for a 0.95 VDC / 60 A supply as illustrated in Figure 1, may simply not be possible.

The engineer should also reference the FPGA device’s datasheet or application note for the specific pin connection guidelines stipulated for the core and transceiver rails. This information provides details regarding line regulation tolerance, its temperature specs, and the transient response required by the device’s individual power rails. It is recommended that attention be paid to determining the choice of regulators required for the FPGA core and the transceivers.

The latest FPGAs and SoCs can require up to 90 A of current and multiple power rails that need careful consideration on power up.
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FPGA, power, rail