Hierarchical Timing Modelling

April 03, 2014 // By Babul Anunay, Freescale Semiconductor

As SoC designers navigate this un-chartered territory and EDA tool vendors strive to match the pace of the VLSI technology drive, hierarchical design is becoming the norm for timing closure. Hierarchical timing helps to close the design with long run-time, large memory foot-print or a block whose design is yet to mature.

With the shrinking of technology to deeper sub-micron levels, SoC design is getting more complex every day since more functionality is getting incorporated into the chips.
hierarchical design, freescale