Method for Safety Compliant Triple Voting Flop Implementation

December 01, 2014 // By Syed Shakir Iqbal, Gaurav Goyal, Abhishek Mahajan

Even with advanced DFT (design for test) architectures, vendors are only able to identify existing faults. Stress testing like burn-in provides a long term predictive stress simulation environment but these tests are also only limited to a few years due to high test costs involved. There are often some critical elements (like register values) within designs that need a higher degree of robustness signoff than those offered by burn-in.

In order to meet these safety or reliability signoffs multi-modular redundancy like a triple voting flip-flop is a very common practice that offers the desired reliability with a minimal cost. Nevertheless, even with additional modular redundancy, designers still end up with blind spots for failures that become a major concern for safety compliant architectures.

This paper proposes a TVF (triple voting flip-flop) architecture that provides a more robust solution against data failures with increased fault coverage. The proposed design also offers a lower rate of failure than conventional TVF designs without any increase in the modular redundancy of existing flip-flops.

In recent years SoC implementation and fabrication processes have progressed through multiple evolutions both due to technological changes as well as design innovations. However, design failures due to silicon defects and other process variations continue to plague the robustness and functionality of fabricated devices leading towards a low yield and high cost of production.
Freescale Semiconductor, triple voting flip-flop