The task of creating Automatic Test Equipment (ATE) test programs for complex digital integrated circuits from the stimulus and response data of Verilog simulations can be challenging. But because this data forms an important part of the device’s functional validation, it is a necessary step in the design-to-test flow for most devices. This paper presents some background information and concepts necessary to understand the criteria which affect the task of translating simulation data to a device test program. It also covers some of techniques that can be used during the design activity to simplify this task.
Verilog, Test, Simulation, Verificatin