20-nm ready for tape out in 2012, says ST
June 07, 2010 // Peter Clarke
STMicroelectronics NV will be ready to tape out designs using a 20-nm CMOS low power process technology in the fourth quarter of 2012, according to Jean-Marc Chery, the company's chief technology officer.
However, ST is not indicating it will ready to make those designs itself, which raises questions about how long ST can rely on its 300-mm wafer fab in Crolles, near Grenoble, France to be its leading-edge R&D and production site.
Chery was speaking at ST's annual analysts's day held here. The company's executives said the company was aiming at 5 to 7 percent capex to sales ratio as part of the "asset lighter" strategy the company is pursuing. It achieved 5.3 percent in 2009. However, that appears to leave no room for ST to ever lay down the several billions of dollars needed to wholly-own a new leading-edge fab.
Whatever does get taped out in a 20-nm design in 2012 is likely to be manufactured first at GlobalFoundries wafer fab in Dresden, Germany or another foundry that is also in the International Semiconductor Development Alliance (ISDA) based around IBM Microelectronics. It could even be one of the first designs to be made at a newly-opened GlobalFoundries fab in New York.
GlobalFoundries is known to be working on a 22-nm process at Dresden which will be used to start operations at the Albany fab that is underconstruction.
"I am very confident we will be able to tape out 20-nm LP in Q4 2012," said Chery. His slide showed that while work on 20-nm is for delivery to ST through an ISDA fab is beginning now in the second quarter of 2010, the same work for delivery through an STMicroelectronics fab is not due to start until Q1 2012.
ST has some processes on its roadmap including general purpose 40-nm and 28-nm that it does not intend to be able to manufacture itself, according to Chery's presentation.
"Beyond 20-nm we will have to change the transistor architecture. Planar will be unable to sustain [suitable operation] below 20-nm." Chery said ST faces a choice between fully depeleted silicon-on-insulator (FD-SOI) and FinFETs. Of course ST will only be a participant in those decisions, which are likely to be taken among the lead manufacturing partners within ISDA.
"Unfortunately you must use double-patterning, which affects productivity." Chery said he expects cost of ownership issues around extreme ultraviolet lithography to be "confirmed" in the third or fourth quarter of this year allowing decisions about a move to EUV lithography to be taken thereafter.
IoT Security Foundation formed
September 04, 2015
The Internet of Things Security Foundation has been formed with a large list of associate members having sprung out of discussions ...
Self-sweeping lasers could make LIDAR systems cheaper
DecaWave preps for expansion, next location chip.
These five trends drive automotive innovation
How to increase your engineering value in just 20 minutes a day
Google-led group preempts HEVC
September 03, 2015
Internet giants Google and Cisco have banded together with Amazon and Netflix, two large streaming service players, along ...
IT security is changing: if the SIEM is dead, what's next?
Serdes startup Credo raises $8 million
The future of print and paper: digital hybrids
- High Voltage CMOS Amplifier Enables High Impedance Sensing with a Single IC
- Software-Defined Radio Handbook
- Why Making the Move from a Variable Transformer to a VariPLUS is the Right Decision
- Automating Leakage and Functional Testing
InterviewCEO interview: Ambiq sees broader options for low voltage
Mike Noonen, recently appointed interim CEO at microcontroller startup Ambiq Micro, discusses the focus and opportunities for this pioneering company designing circuits that can operate below the threshold ...
Filter WizardCheck out the Filter Wizard Series of articles by Filter Guru Kendall Castor-Perry which provide invaluable practical Analog Design guidelines.
Linear video channel
READER OFFERRead more
This month, Altera is giving away three of its second-generation Nios II Embedded Evaluation Kit (NEEK), worth 9 each, for EETimes Europe's readers to win.
The feature-rich platform provides a fast and simple way for embedded designers to experience the capabilities of a custom embedded processor in a non-volatile FPGA.
MORE INFO AND LAST MONTH' WINNERS...
December 15, 2011 | Texas instruments | 222901974
Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.