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3D packaging takes a key step forward as TSMC tapes out CoWoS chips

October 12, 2012 // Nick Flaherty

3D packaging takes a key step forward as TSMC tapes out CoWoS chips

Fabless chip companies will have more design options for 3D integration and smaller footprint packaging as TSMC tapes out its first CoWoS (Chip on Wafer on Substrate) test chips using the JEDEC Wide I/O mobile DRAM interface.

The milestone demonstrates the industry’s system integration trend to achieve increased bandwidth, higher performance and superior energy efficiency by mounting the DRAM directly on the logic chip as a substrate using the Wide I/O interface.
TSMC’s CoWoS technology provides the front-end manufacturing through chip on wafer bonding process before forming the final component. Along with Wide I/O mobile DRAM, the integrated chips provide optimized system performance and a smaller form factor with significantly improved die-to-die connectivity bandwidth.
CoWoS is an integrated process technology that attaches silicon chips to a wafer through chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component and the technology has now entered the pilot production stage.
Key to the tapeout is the ecosystem with Wide I/O DRAM coming from SK Hynix, Wide I/O mobile DRAM IP from Cadence Design Systems and EDA tools from Cadence and Mentor Graphics.
The design flow includes the management of placement and routing of bumps, pads, interconnections, and C4 bumps; innovative combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated 3D testing methodology for die-level and stacking-level tests.
“Silicon validation is a critical step in the development of a highly advanced and complete CoWoS design solution,” said Cliff Hou, Vice President of Research and Development at TSMC. “The successful demonstration of the JEDEC Wide I/O mobile DRAM interface highlights the significant progress TSMC and its ecosystem partners have made to capitalize on the performance, energy efficiency and form factor advantages of CoWoS technology.”
”TSMC and Cadence have worked together to validate the industry’s first design IP for Wide I/O in TSMC’s CoWoS process,” said Martin Lund, Senior VP of Research and Development for the SoC Realization Group at Cadence. “Our design IP is capable of over 100Gbit/sec of DRAM bandwidth at very low power when connected to Wide I/O devices meeting the JEDEC JESD229 Standard.”

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