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7nm EUV could ease 10nm squeeze, says ASML

7nm EUV could ease 10nm squeeze, says ASML

Technology News |
By eeNews Europe



However, that will make the 10 nm node an unpopular one that is pressed to deliver lower costs per transistor. Most critical layers will require three or even four exposures, said ASML president and chief technology officer Martin Van den Brink in a 90-minute interview here.

“10 nm will be a squeezed node that no one will like, due to insufficient cost reduction, but there will be enough cost reduction to let it go forward,” Van den Brink said.

For the follow-on 7 nm generation, chipmakers will need to use EUV to make chips cost effectively, he insisted. Without it some layers would require as many as 13 passes through an immersion stepper, he told us.

Without EUV, the 7nm node (far right) could require patterning some layers as many as 13 times, ASML claims. The 10nm node (second from right) will need triple and quad patterning at many layers, Van den Brink said.

Without EUV, the 7nm node (far right) could require patterning some layers as many as 13 times, ASML claims. The 10nm node (second from right) will need triple and quad patterning at many layers, Van den Brink said.

Van den Brink made his comments at the ASML office just a block away from the headquarters of one of his largest customers, Intel. Last week, Intel Fellow Mark Bohr said the CPU giant has found a way to make its 7 nm chips without EUV.

“My full-time job is researching 7 nm, and I would like to have [EUV] but I cannot bet my career or Intel’s future on it… [and] 7 nm is doable in my opinion without EUV.”

Some are skeptical of Intel’s assertion it is achieving higher resolutions than its competitors using the same lithography equipment. Even one Intel process technology manager once expressed to EE Times it is sometimes unclear why a particular process is associated with one node as opposed to another.

The way nodes get named has become opaque given the rising complexity of the underlying processes, he said. “It’s all part of the marketing today — it’s too convoluted.”


EUV makes slow progress

ASML aims to match litho targets to the silicon road map.

ASML aims to match litho targets to the silicon road map.

Mask makers need to ramp up support for EUV by 2016 when many chip makers will start qualifying EUV systems on a 10 nm process, Van den Brink will tell an audience of mask makers in a keynote on September 16. Fabs will test out EUV at 10 nm but not put it into production until they ramp their 7 nm nodes, he told EE Times. Nevertheless the tools promise a lifetime of at least a decade.

“Masks are at much lower volumes than wafers, so mask makers are vulnerable to appetite changes in the industry, and they are more conservative, hence showing our progress to mask folks is important to encourage [their EUV] development.”

EUV still faces several challenges, the biggest of which is the need for a reliable, higher-power light source to drive throughput to a target of at least 1,000 wafers a day. Van den Brink says ASML currently has an EUV system running in its lab with a 77 W light source.

By the end of the year, the company expects to have an 80 W light source working, twice as powerful as the 40 W source its customers are using today. The 80 W light source will be a key component to a 3350B system it will supply to key customers next year.

ASML is on target to deliver an 80W EUV system in 2015.

ASML is on target to deliver an 80W EUV system in 2015.

The 3350B will ultimately hit 1,000 wafers a day — a threshold for commercial use — although customer systems may only deliver 800 wafers a day at first. ASML plans multiple upgrades of the optics and software that will enable its use at 7 nm by focusing the EUV light to increasingly refined fractions of a die.

In 2015 and beyond, ASML foresees upgraded optics and software for EUV.

In 2015 and beyond, ASML foresees upgraded optics and software for EUV.

At the end of the day, an EUV system capable of production use at 7 nm could cost $100 million to $120 million, twice the price of traditional immersion steppers. Van den Brink notes the designs are modular so that customers with earlier prototypes can upgrade them in stages.


More details on EUV progress

EUV systems also need to reduce mask defects. Defects in blank masks have been reduced to zero (above). But “as long as there is one defect particle [in patterned masks], there is a fear, so we started developing pellicles,” says Van den Brink.

Immersion systems have long depended on the protective layers, but developing them for EUV is still a work in progress. ASML has demonstrated an 85% transmissive pellicle mounted on half an EUV mask without significant impact on wafer imaging (below).

ASML is in progress with a test of a pellicle that covers the entire mask. However Van den Brink made clear the company’s goal is to enable defect-free masks without a pellicle. If the industry wants a protective layer, it should come from mask makers, he suggested.

“We will continue developing this pellicle, but we are willing to transfer the technology to [third-party] vendors,” although so far there have been no takers.

Van den Brink also reported on progress developing chemically amplified resists (bottom) and in testing a variety of resist chemicals. Some of the resists have degraded EUV images, but Van den Brink expressed optimism that “substantial innovations will come.”

— Rick Merritt is Silicon Valley Bureau Chief at EE Times


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