Using 10-Gbps Transceivers in 40G/100G Applications
September 06, 2011 // Rishi Chugh, Altera // 0 commentsDownload White Paper 602Ko
This white paper identifies the key drivers behind the migration to 100G interfaces, and shows how to leverage the unique ability of FPGAs to implement this high-speed interface. The emerging 40GbE and 100GbE standards for data center and core network systems rely heavily on FPGAs to share those sectors with other protocol infrastructures. In addition to providing an unprecedented amount of resources such as logic, on-chip memory, and DSP blocks, Stratix IV devices are the only FPGA family to enable these 40G/100G designs, which require 10G transceiver data rates with extraordinarily low jitter performance to meet high-speed design requirements.
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The SoCKIT evaluation kit is Arrow's latest development tool, featuring an Altera Cyclone V SoC with a dual-core ARM Cortex-A9 MPCore processor integrated within its 28nm FPGA fabric.
Altera SoCs allow embedded system developers to differentiate their end product with customized hardware and software, and extend the product lifecycle through hardware and software updates in the field. This month, Arrow Electronics is giving away five SoCKIT evaluation kits featuring Altera’s ARM-Based SoCs, worth €249 each, together with the free entrance to one of Arrow’s SoC workshops organized throughout Europe.
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