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Using 10-Gbps Transceivers in 40G/100G Applications

September 06, 2011 // Rishi Chugh, Altera // 0 comments

Using 10-Gbps Transceivers in 40G/100G Applications Download White Paper 602Ko

This white paper identifies the key drivers behind the migration to 100G interfaces, and shows how to leverage the unique ability of FPGAs to implement this high-speed interface. The emerging 40GbE and 100GbE standards for data center and core network systems rely heavily on FPGAs to share those sectors with other protocol infrastructures. In addition to providing an unprecedented amount of resources such as logic, on-chip memory, and DSP blocks, Stratix IV devices are the only FPGA family to enable these 40G/100G designs, which require 10G transceiver data rates with extraordinarily low jitter performance to meet high-speed design requirements.


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This month, Future Electronics has 20 of Intersil's ISL8203MEVAL2Z evaluation boards to give away to EETimes Europe's readers. Worth 95 US dollars, the board was designed to demonstrate the performance of the ISL8203M dual step-down power module which integrates a PWM controller, synchronous switching MOSFETs, inductors, and passives all in a 9.0x6.5x1.83mm package.

The ISL8203M is rated for dual 3A output current or 6A current sharing operation with an input range of 2.85V to 6V. Each of the two channels employs the current mode pulse width modulation scheme for fast transient response and pulse-by-pulse current limiting.

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