3-D IC standards needed within six months
February 01, 2012 // Rick Merritt
Standards for 3-D chip stacks need to be in place within six months to stay ahead of chips rolling out in 2013, said a Qualcomm executive driving some of the efforts.
The good news is Jedec released in early January an initial standard for Wide I/O memories seen as key for mobile application processors. The bad news is some standards efforts, including faster Jedec memories needed for server and networking uses, may drag into 2013.
“We have less than a year to put the rest of the key standards in place, otherwise commercial pressures will push EDA and other companies to solve the problems themselves and want to own their solutions,” said Riko Radojcic, a director of advanced technology engineering at Qualcomm, speaking in a panel discussion on the topic at DesignCon here.
“I think we have a window of opportunity that of months,” said Radojcic who chairs a board overseeing a set of 3-D IC standards efforts underway at the Silicon Integration Initiative Inc., (Si2), an industry standards group. “Those of us who are impatient think we are already a year behind,” he said.
The Si2 effort consists of three working groups officially kicked off last summer at the Design Automation Conference. The groups are expected to deliver by the end of this year standards for the first of three phases, said Sumit DasGupta, senior vice president of engineering at Si2.
The initial phase is defining formats for sharing design data on 2.5- and 3-D partitioning and floor planning including thermal and mechanical constraints and exclusion zones between chip layers. A second phase will create formats for sharing modeling information, and a third phase will describe formats and APIs needed to create full 3-D IC design flows, he said.
The Si2 group includes participants form Cadence, Intel, GlobalFoundries, Mentor Graphics and Qualcomm among others. “Our goal is to deliver the first specs for review late in the second or third quarter,” said DasGupta.
Separately, Sematech has kicked off a variety of manufacturing standards listed on its Web site. They include definitions for process flows, thermal and mechanical strength standards and underfill materials, said Raj Jammy, vice president of emerging technologies at Sematech.
“Some standards will be done this year, some are likely to get done next year and we think the basic standards will have to be wrapped up fairly soon,” said Jammy.
Several elements are still missing, said Liam Madden, a corporate vice president at Xilinx that announced in October a 2.5-D chip laying multiple FPGA die on a common substrate. He called for more companies to get involved in next-generation Jedec standards for Wide I/O memory running at terabit/second rates.
“The current standard is for a couple hundred Gbits/s — t’s a great start and will drive innovation in mobile, but if look at data center apps, we need another level beyond that,” he said.
According to a recent Intel presentation, Jedec has two groups working on next-generation Wide I/O standards. One group targets an eight-fold increase in the bandwidth of the initial spec with explicit support for 2.5- and 3-D stacks. A “high bandwidth memory” group is working on a follow-on standard for graphics, networking and high-performance computing, currently evaluating a 1,024-bit link, the Intel presentation said.
Among other missing pieces, Madden of Xilinx said the industry has yet to kick off an effort for stacking mixed-signal, optical and digital components. “If we are going to get to next level, that’s what I’d like to see addressed,” he said.
The industry also needs manufacturing standards for when and how work gets passed from fabs to packaging companies, Madden said. “In one example, we couldn’t send anything to anyone,” he said.
That’s a particularly thorny issue because “it’s not clear who will do much of the work and so far through-silicon via fabrication and polishing is something [packaging companies] are generally not in a position to do today,” said Jimmy of Sematech.
Radojcic of Qualcomm agreed there needs to be an effort to define how to handle stacks of analog and digital die. “Maybe analog companies need to come up with a killer app for analog-on-digital stacking, because there is nothing going on there today,” he said.
“The first thing I’d like to see is Wide I/O stuff because it drives the entire ecosystem,” said Jim Hogan, a veteran EDA executive turned private investor.
Overall, Hogan warned standards groups not to define formats too precisely.
“We don’t know how [3-D stacks] will work out,” he said. “They will become a convention after awhile, but I am trying to prevent things from becoming too complicated,” he said.
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