Modeling stress-induced variability at advanced IC process nodes
May 14, 2012 // By Philippe Hurat and Fang-Cheng Chang
As design teams move to IC process nodes at 40nm and below, timing and power variability become more and more of a concern. To maximize system performance and meet timing and power goals, designers must find ways to model and mitigate variability.
A leading cause of systematic variability at advanced process nodes is the application of mechanical stress to transistors – even when the stress is applied intentionally to enhance performance in CMOS ICs. At 28nm and 20nm, in particular, design flows and EDA signoff tools must be able to analyze and mitigate stress-induced variability.
Read the full article on page 34 of our May digital edition.All news
Iron fluoride to triple energy storage?
April 21, 2015
Researchers the University of Wisconsin–Madison and Brookhaven National Laboratory have developed a novel X-ray imaging technique ...
EMEA PC shipments resume steady decline
Nohau to resell Icon Labs' security portfolio in Scandinavia
Distribution deal for Silex Technology wireless connectivity, with Arrow
MIT accessorizes your thumbnail with track pad
MINI giving drivers a peek at 'augmented reality'
April 20, 2015
Although most drivers have yet to embrace the idea of head-up displays (HUDs) on windshields, MINI is leapfrogging to the ...
Moore's Law: a mixed-signal perspective
Connected LED opens path to 'intelligent cities'
Magnesium ions for car batteries
- Smart Capacitive Design Tips
- Wireless MCUs and IoT
- Battery Management System Tutorial
- Deciding if Automated Test is right for your Company
InterviewInfineon: CAN FD success goes at the expense of FlexRay
The faster version of the venerable CAN bus, CAN FD is currently taking off at several carmakers. Infineon's Thomas Böhm, Head of Body / Automotive, believes this could well go at the expense of FlexRay. ...
Filter WizardCheck out the Filter Wizard Series of articles by Filter Guru Kendall Castor-Perry which provide invaluable practical Analog Design guidelines.
Linear video channel
READER OFFERRead more
This month, DecaWave is offering EETimes Europe's readers the chance to win two TREK1000 kits to evaluate its Ultra-Wideband (UWB) indoor location and communication DW1000 chip in different real-time location system topologies.
Worth €947, the kit allow designers to prove a concept within hours and have a prototype ready in days. Based on the two-way ranging scheme, the kit lets you test...MORE INFO AND LAST MONTH' WINNERS...
December 15, 2011 | Texas instruments | 222901974
Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.