Modeling stress-induced variability at advanced IC process nodes
May 14, 2012 // By Philippe Hurat and Fang-Cheng Chang
As design teams move to IC process nodes at 40nm and below, timing and power variability become more and more of a concern. To maximize system performance and meet timing and power goals, designers must find ways to model and mitigate variability.
A leading cause of systematic variability at advanced process nodes is the application of mechanical stress to transistors – even when the stress is applied intentionally to enhance performance in CMOS ICs. At 28nm and 20nm, in particular, design flows and EDA signoff tools must be able to analyze and mitigate stress-induced variability.
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