STMicroelectronics and Soitec cooperate to deliver 28nm FD-SOI CMOS process
October 19, 2012 // Julien Happich
STMicroelectronics, Soitec and CMP (Circuits Multi Projets) have announced the availability of ST's CMOS 28nm fully depleted silicon-on-insulator (FD-SOI) process for prototyping.
The process is made available to universities, research labs and design companies through the silicon brokerage services provided by CMP. ST is releasing this process technology to third parties as it nears completion of its first commercial wafers.
The introduction in CMP’s catalogue of ST’s 28nm FD-SOI CMOS process builds on the successful collaboration that has allowed universities and design firms to access previous CMOS generations including 45nm (introduced in 2008), 65nm (introduced in 2006), 90nm (introduced in 2004), and 130nm (introduced in 2003). CMP’s clients also have access to 65nm and 130nm SOI (Silicon-On-Insulator), as well as 130nm SiGe processes from STMicroelectronics.
For example, 170 universities and other companies have received the design rules and design kits for the ST 90nm CMOS process, and more than 200 universities and companies have received the design rules and design kits for the ST 65nm bulk and SOI CMOS processes.
Since CMP started offering the ST 28nm CMOS bulk technology in 2011, some 60 universities and microelectronics companies have received the design rules and design kits and 16 integrated circuits (ICs) have already been manufactured.
The CMP multi-project wafer service allows organizations to obtain small quantities--typically from a few dozens to a few thousand units--of advanced ICs. The cost of the 28nm FD-SOI CMOS process has been fixed to 18,000 €/mm2, with a minimum of 1mm2.
“With the first designs in FD-SOI technology already in the pipeline, the time is right to make the technology available to the research communities. Our FD-SOI manufacturing process allows existing designs to be quickly and easily ported to FD-SOI where significant power and performance benefit can be realized,” said Philippe Magarshack, Executive Vice President, Design Enablement and Services, STMicroelectronics. “In addition, ensuring that universities have access to our leading-edge technologies can help us attract the best young engineers as part of our commitment to remain a technology leader on a long-term basis.”
Visit STMicroelectronics at www.st.com
Visit Soitec at www.soitec.com
Visit CMP at http://cmp.imag.frAll news
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