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Algotronix adds thermal signaling to IP core DesignTag

July 18, 2008 //

Algotronix Ltd. (Edinburgh, Scotland), has added 'thermal signaling' to DesignTag, an active digital circuit element that can be designed-in to ICs and FPGAs and detected through-package by an external scanner.


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LONDON Algotronix Ltd. (Edinburgh, Scotland), has added 'thermal signaling' to DesignTag, an active digital circuit element that can be designed-in to ICs and FPGAs and detected through-package by an external scanner.

Algotronix, a consultancy spun out of Xilinx in 1998, has been offering DesignTag for over a year. DesignTag is intended to provide a method of identifying falsely labeled chips and supporting enforcement of IP core and CAD tool license agreements.

DesignTag is a digital core coded with a customer-specific signature' that can be identified externally from a working device without needing to read the FPGA bit stream or take the chip out of its package. It works by modulating the power dissipation of the host device by around 5mW which creates small temperature changes which are sensed by a thermocouple and decrypted by the reader software running on a PC.

Single or multiple tags can be present in a single chip and the scanner can read the serial number of each tag and use a separate web-based database to find out about a tagged chip. Security mechanisms allow DesignTag users to control who can detect their tag or to restrict elements of the information stored in the web database.

According to Algotronix the use of wirelessly readable tags would allow providers of IP cores to increase recognition for their work and increase the value of their cores and businesses. At present chip labeling is done in ink at the final stages of manufacture and recognizes the IDM that physically makes the system-chip (SOC) or the maker of the FPGA, but not the IP contributors.

"The problem is how to deter theft and prove ownership of the design, said Tom Kean, managing director of Algotronix, in a statement.



The tag can also be used to confirm the design revision loaded into the FPGA or to signal internal status conditions, such as, when an overflow has occurred or a soft error was detected in memory. Signaling is done without interrupting the system operation or accessing package pins.

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