The growing demand for cheap consumer wireless applications calls for unprecedented levels of integration. Huge digital IPs, such as microprocessors, digital signal processors, or encryption engines, are being assembled together with analog blocks * e.g. power supply control, data conversion * and radio-frequency (RF) * LNA, VCOs, mixers.

The former, also known as the aggressor, generates lots of interfering noise, which gets disseminated through the entire system to finally degrade the operation of the most sensitive circuitry (the victim).

The entire electrical signal integrity (ESI) mechanism is very complex. It affects digital operation through IR drop, cross-talk and delay, as well as analog and RF. For the latter, the impact is rather more complicated as very small noise level will produce dramatic influences at any time * and not only in the neighborhood of specific signal transitions as occurs in the digital domain.

Many scientific publications and commercial software solutions are addressing the impact of ESI on digital design. The remainder of this paper will therefore focus on analog/RF impacts.

In summary, noise impacting analog and RF victims is produced by circuits manipulating large electrical signals at high frequencies. These aggressors are any combination of digital, analog or RF functions drawing significant amounts of current on the power supplies which, because of the various physical interconnect and package parasitics involved, result in considerable supply bounce.

In addition, as illustrated in Figure 1, substrate noise injection happens across a wide range of various mechanisms * conductive through device bulks and substrate biasing contacts, capacitive from source-drain junctions or metal capacitances, in conjunction with well-substrate junctions. The noise disseminating across the whole system is further filtered when transferred through the RC substrate coupled to the RLC parasitics from both interconnect and package. The same parasitics also prevent a perfect grounding of sensitive circuitry, and a significant amount of noise eventually reaches victim devices through a combination of substrate, interconnect and package parasitics.

Amongst all the challenges to address ESI impact on analog and RF victims, modeling noise generation and injection is particularly tricky. The issue is to collect the many power supply and substrate currents in both time and frequency domains. Figure 2 illustrates a sample for the simplest possible cell: a CMOS buffer. The contribution here is for one specific set of input slew rate and output load conditions. In real life this has to be conducted over a wide range of operating settings, for all families of each cell in a standard library.

On one side, existing noise models available in popular EDA flows * such as ECSM * tackle only power supply noise in the time domain. On the other side, recent publications considering analog/RF impact focus on substrate noise modeling, and are not compatible with the requirements of commercial software. In addition, interconnect is not the dominant and only cross-talk medium, unlike in purely digital applications. For analog and RF applications, as depicted in Figure 3, the simulation of noise propagation with various substrate types exhibits the comparable importance of capacitive and inductive coupling through interconnects and package above 1 GHz.

Moreover, the impact of interfering noise on analog and RF victims is not limited to delay but ranges from poor biasing to full specification degradations * such as the noise figure of LNAs, phase noise and spurs on VCOs, etc. * that require noise modeling capabilities both in the time and frequency domains. To add even greater complexity, of course the respective impact of substrate, interconnect and package parasitics depends on the manufacturing being used, the design style * which in turn relates to the standard cells being used * and system specifications targeted.

At the end of the day, only a dedicated software platform can help to address, effectively, ESI issues to detect system weaknesses early enough in the design flow and to determine the most appropriate solution.

One can summarize the high-level requirements for an EDA solution to ESI as follows:

- Ability to model any silicon and package manufacturing technology, - Pre-characterization of standard cell library contributions, - Unified modeling technology to process complex IPs as well as full systems, from early floorplanning to final layout verification, - Seamless integration into most popular design flows.

The Coupling Wave Solutions (CWS) answer is a software platform called WaveIntegrity. As shown in Figure 4, all four tools comprising this set are based on common extraction and analysis engines. Dedicated to manufacturing data characterization, WaveMapper extracts parameters necessary to model, accurately, substrate and interconnect parasitics. WaveLibrarian automatically processes standard cell, core and I/O cell libraries to generate compact proprietary models, adding ESI to the set of existing cell descriptions. WaveModeler is a versatile IP block modeling tool that allows IP providers to communicate ESI parameters without giving out the heart of their intellectual property. WaveAnalyst is an investigation solution which helps designers to analyze and enhance the robustness of complex systems and IP blocks, from RTL to final layout sign-off.

For maximum performance and capacity, WaveMapper and WaveLibrarian are used to collect the most important characteristics driving the injection and propagation of noise.

WaveMapper is run once for every process to extract the substrate and interconnect characteristics necessary for the 2.5D extraction engines. Besides the significant extraction speed-up benefit provided by this pre-processing, the technology mapper brings an increased protection to commercially very sensitive foundry IP by compacting doping profiles into information that prevents reverse engineering. WaveLibrarian automatically reads behavioral and spice descriptions, together with abstract and full layouts of standard cells, to compute a proprietary ESI macro-model. This includes noise contribution in the form of power supply and substrate sources, as well as a passive RC model providing a link between all sources and the cell periphery * see Figure 5.

During the characterization process, many noise figures are collected. To speed up system level analysis and at the same time limit the size of the final data base, a reduced set of harmonic equivalents * such as the one shown in Figure 6 * is eventually stored. This simplification mechanism allows efficient reconstruction in time and frequency domains during complex IP or full system analysis while preserving the precision level.*

For each cell, the exhaustive set of injection conditions is explored by varying input vectors and input slopes as well as output loads. At the end of all simulations, a proprietary algorithm allows the determination of the worst, and least injection figures, as well as a statistical typical behavior. Significant challenge

A significant challenge in modeling noise generation, from early in the design flow to final layout, is the varying level of details available.

The most detailed data is only obtained at the final stage, when many kinds of information are accessible * physical layout with final placement and routing, signal delays and gate loads * through various standard formats (GDSII, DEF, LEF, SPEF, DSPF É).

Adversely, before entering the physical system assembly, the available information can be as limited as approximated number of gates and estimated area, as well as power supply and clock domain assignments. To overcome the lack of detailed information at this stage, specific algorithms are necessary to provide an estimation of noise in these conditions.

Of course, as depicted in Figure 7, the level of accuracy will vary, reaching the best possible model only when the final layout is known. For instance, it is not possible to assess the exact operation conditions (delay, gate loads) until the final layout.

Even before, early in the flow, the detailed netlist is not known, adding more uncertainty to the noise injected by a particular IP block. Therefore, a specific methodology is required to overcome the limited accuracy available early in the flow.

The CWS answer to system noise model utilizes the pre-characterized standard cell data to propose, independent of the level of detail provided, three noise representations: worst, typical and best noise figure.

Thanks to the application of a common set of technologies throughout the flow, the worst and best case estimation will converge when the physical description gets closer to the final layout.

CWS noise modeling algorithms take advantage of the statistical information that might be extracted from existing designs (typical cell usage, statistical delay and load distribution, etc.). Later on, as detail becomes known, estimations are replaced with actual data and the whole system description is processed using the same technologies. This method ensures the necessary convergence of worst and best cases toward the typical noise obtained only after final layout.*

This way, noise can be estimated far before the physical implementation to help in making critical decisions. In fact, if worst case noise analysis does not raise any ESI issues, it is safe to carry on, and very likely that first silicon will be free of cross-talk. Adversely, if best case estimation flags potential interference concerns, proceeding to physical implementation is extremely risky and severe corrections are required which might motivate high-level choices such as package, architecture, etc.

The propagation model is automatically computed from a layout description. The resulting netlist * combining self and mutual RLC parasitics of substrate, interconnect and package * can be explored using a dedicated visual aid as depicted in Figure 8.

This transfer function is pulled together with the system level noise to save a comprehensive model of interfering noise. Therefore, a proprietary analysis engine simulates the amount of noise reaching user-defined monitoring nodes in the system. The output can be visualized in the time and frequency domains as demonstrated in Figure 9.

In the past, before any software solution was available, all failures related to interference in mixed digital/analog/RF systems were detected by measurement; moreover finding and fixing the issues was extremely uncertain. Yet, the availability of early noise estimation can not always prevent iterations from final layout back to functional re-design.

Because functional simulators lack the actual descriptions of noise reaching victim blocks, re-spins occurs over lengthy and tedious re-design loops encompassing functional and physical implementation * see Figure 10 (a).

The solution provided by CWS is to automate the feedback of noise figures computed during ESI analysis within popular functional simulators * such as Eldo, EldoRF, Spectre or the like. As a result, it is now possible to assess the victim's immunity to actual noise. Existing circuit design techniques can therefore be applied more effectively during function implementation to reach the best possible noise margin. As pictured in Figure 10 (b), the physical implementation loop thus has a dramatically greater chance of concluding ESI analysis successfully.

In addition, WaveIntegrity incorporates calibration mechanisms which bring improved high-level noise estimation after silicon failures. This feature is yet another key factor to ease the investigation and to increase the effectiveness of solutions to the most difficult ESI problems.

As an application example of the automated back-annotation, the simulation of parasitic noise spurs produced on a LC-tank VCO is presented in Figure 11.

Detecting ESI issues is critical but not sufficient. Whenever interfering noise monitored with WaveAnalyst * and/or back-annotated within functional simulation * demonstrates unacceptable electrical behavior, one faces a tedious investigational challenge.

One aspect is covered using the back-annotation to improve the victim immunity with respect to the back-annotated interfering noise.

Another aspect is to decrease noise generation and propagation. Within WaveAnalyst this investigation process is helped thanks to a couple of dedicated post-processing engines. The graphical explorer depicted in Figure 8 allows designers to visualize the propagation geometry and to explore the parasitic netlist. This helps to solve the most obvious design errors, such as incorrect connection of isolation structures (open circuits, shorts with noise interconnects) as well as power supply grid problems.

In addition, for each monitoring node, a list of major aggressors, sorted by order of decreasing influence, can be produced. With this inventory, it is possible to identify a limited set of noise injectors whose influence must be decreased. This can be achieved by applying various known design techniques * selection of low noise alternates, use of separate power supplies, relaxation of clocking. Last but not least, when the former solutions have been applied but the noise reduction is not sufficient, the transfer function from one single noise source to a specific monitoring node is analyzed to determine the most effective corrective action: addition/modification of guard rings, use of manufacturing features (triple wells).

When all techniques above have failed, then the system might not be feasible without a dramatic change such as selecting a more expensive package, or entering system and architecture re-design.

Following is an application of WaveIntegrity describing the operations involved in investigating and solving ESI issues.

This example unfortunately occurred on real silicon after several months of production and measurement. The problem detected in the test lab is summarized in Figure 12 (a). In this diagram, the noise level reaching victim blocks with various isolation strategies is plotted versus frequency. It appears that the supposedly best isolation structure * i.e. O8 grounded ring in Figure 12 * is failing above 10 MHz, reaching a level of noise on the victim similar to the one measured on unprotected blocks beyond 100 MHz.

As exhibited in Figure 12 (b), WaveAnalyst output after modeling and analyzing this design catches correctly the isolation issue raised by the measurement data. The analysis time is 22 minutes on a PC running RedHat Entreprise Linux 3.0 on a P4 processor clocked at 3 GHz with 2Gb of RAM. Next, the failure is further investigated using WaveIntegrity post-processing tools. In this particular case, the visualization of the propagation geometry offers a quick and clear explanation, as illustrated in Figure 13.

In this graphical helper, it is possible to see each power supply domain with a different color. Adversely to conventional circuit extractors, which consider the substrate as ideal, two interconnect geometries pertain to the same power supply net only if there exists a metal connection between them. As a consequence, the metal shapes used to bias the substrate of particular cells would be considered a different net than the ones used to bias guard rings if the power is brought on-chip through distinct pads (even though the two signal might connect off-chip to the same electrical potential).

In our practical example, it was a surprise to observe the inner pad ring and the isolation biasing share the same color. As a matter of fact, the inner pad ring is used to feed all ESD structures and is known to carry a significant level of noise. Contacting this net together with the isolation structures brings a lot of problems instead of increasing the immunity.

After the explanation provided by WaveIntegrity, the design was corrected and a new 20 minute analysis verified that the isolation was restored to its expected level, as demonstrated in Figure 14.

ESI issues, occurring when assembling RF and/or analog circuits on the same die or within the same package as inherently noisy blocks (such as large digital processing functions), are extremely complex.

Such issues traverse many design phases * are not restricted to the final physical implementation * and often involve designers with very different levels of expertise (analog, RF and digital at system and block levels).

Overall, the many post-analysis tools within WaveIntegrity offer a powerful guide to detect, fix and verify ESI issues through effective what-if analysis before entering the costly production stage. The level of automation involved in the tool allows any designer to get quickly up to speed, even with very limited expertise.

Moreover, the automatic back-annotation of interfering noise within functional simulation provides an easy (and welcome!) communication channel between digital, analog and RF designers.

* Patent's are pending on this technology.

Francois Clement (Francois.Clement@cwseda.com) is chief technology officer at Coupling Wave Solutions (Grenoble, France).