Print  |  Send  |   

Automated FPGA to ASIC Conversion with Zero NRE

February 09, 2011 // Gal Gilat, KaiSemi Ltd. // 0 comments

Automated FPGA to ASIC Conversion with Zero NRE Download White Paper 326Ko

FPGA design suits a fast time-to-market product, while its chip cost is high. ASIC design or traditional FPGA to ASIC design involve high resources cost, while the chip cost is low. This paper presents a smooth automated conversion from FPGA to ASIC which is seamless to customer resources, while being dedicated to cost optimization. FPGA cost overheads are tackled by addressing three aspects: redundant die area, pricing of various fab process and production material.The paper analyzes the risks, complexity, lead-times and costs involved with FPGA and FPGA-to-ASIC conversion options.


All White Papers


Submit a white paper

Follow us

Fast, Accurate & Relevant for Design Engineers only!

Technical papers     

Linear video channel

READER OFFER

Read more

This month, Arrow Electronics is giving away ten BeMicro Max 10 FPGA evaluation boards together with an integrated USB-Blaster, each package being worth 90 Euros, for EETimes Europe's readers to win.

Designed to get you started with using an FPGA, the BeMicro Max 10 adopts Altera's non-volatile MAX 10 FPGA built on 55-nm flash process.

The MAX 10 FPGAs are claimed to revolutionize non-volatile integration by delivering advanced processing capabilities in a low-cost, instant-on, small form factor programmable logic device.

MORE INFO AND LAST MONTH' WINNERS...

Design centers     

Automotive
Infotainment Making HDTV in the car reliable and secure

December 15, 2011 | Texas instruments | 222901974

Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.

 

You must be logged in to view this page

Login here :