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Automated FPGA to ASIC Conversion with Zero NRE

February 09, 2011 // Gal Gilat, KaiSemi Ltd. // 0 comments

Automated FPGA to ASIC Conversion with Zero NRE Download White Paper 326Ko

FPGA design suits a fast time-to-market product, while its chip cost is high. ASIC design or traditional FPGA to ASIC design involve high resources cost, while the chip cost is low. This paper presents a smooth automated conversion from FPGA to ASIC which is seamless to customer resources, while being dedicated to cost optimization. FPGA cost overheads are tackled by addressing three aspects: redundant die area, pricing of various fab process and production material.The paper analyzes the risks, complexity, lead-times and costs involved with FPGA and FPGA-to-ASIC conversion options.


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The development platform for i.MX 6Quad from element14 (built to the Freescale SABRE Lite design) is an evaluation platform featuring the powerful i.MX 6Q, a multimedia application processor with Quad ARM Cortex-A9 cores at 1.2 GHz from Freescale Semiconductor.

This month, Freescale and element14 are giving away five such platforms, worth £128.06 each, for EETimes Europe's readers to win. The platform helps evaluate the rich set of peripherals and includes a 10/100/Gb Ethernet port, SATA-II, HDMI v1.4, LVDS, parallel RGB interface, touch screen interface, analog headphone/microphone, micro TF and SD card interface, USB, serial port, JTAG, camera interface, and input keys for Android. 


 

And the winners are...

In our previous reader offer, Pico Technology was giving away one of its recently launched PicoScope 3207B, a 2-channel USB 3.0 oscilloscope worth 1451 Euros. Lucky winner Mr L. Sanchez-Gonzalez from Spain should be receiving his PicoScope 3207B soon. Let's wish them some interesting findings with his projects.


 

 

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