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Automated FPGA to ASIC Conversion with Zero NRE

February 09, 2011 // Gal Gilat, KaiSemi Ltd. // 0 comments

Automated FPGA to ASIC Conversion with Zero NRE Download White Paper 326Ko

FPGA design suits a fast time-to-market product, while its chip cost is high. ASIC design or traditional FPGA to ASIC design involve high resources cost, while the chip cost is low. This paper presents a smooth automated conversion from FPGA to ASIC which is seamless to customer resources, while being dedicated to cost optimization. FPGA cost overheads are tackled by addressing three aspects: redundant die area, pricing of various fab process and production material.The paper analyzes the risks, complexity, lead-times and costs involved with FPGA and FPGA-to-ASIC conversion options.


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This month Ambiq Micro is giving away five of its 'Apollo EVB' evaluation boards, worth 9 each for EETimes Europe’s readers to assess the capabilities of their cutting-edge Apollo sub-threshold microcontroller.

The new suite of Apollo MCUs is based on the 32-bit ARM Cortex-M4 floating point microcontroller and redefines 'low power' with energy consumption that is typically five to ten times lower than that of MCUs of comparable performance (thanks to Ambiq’s patented Subthreshold Power Optimized Technology platform).


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