Cadence adds new capabilities to PCIe VIP including PIPE4 support to boost performance

July 12, 2012 // Paul Buckley

Cadence Design Systems, Inc. has released new capabilities in its PCI Express Verification IP (PCIe VIP) which result in more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels.

The Cadence technology includes support for the new PCIe PIPE4 specification; new performance measurement features critical for optimizing PCIe implementation; TripleCheck test suite, coverage and verification plan to shorten and ease testing for full PCIe specification compliance; and Accelerated PCIe VIP that drives the verification speed required for large SoCs.

The release addresses the full spectrum of PCIe applications and supports the latest specifications, including SR-IOV, MR-IOV, NVMe and PIPE4, empowering customers to implement designs quickly and confidently incorporating the newest PCI Express interfaces.

Already used on hundreds of production designs, the Cadence PCIe VIP enables efficient and thorough verification of SoCs.  A new performance measurement utility helps customers optimize their designs for improved link utilization, throughput, latency, and power.  The PCIe TripleCheck IP Validator, Cadence’s third-generation compliance solution, verifies that IP blocks comply fully with protocol specifications.  TripleCheck combines the three most critical components of verification in a single, easy-to-use environment: a test suite, coverage model, and verification plan covering all sections of the PCIe specification including PL, DLL, TL, Power Management and Error Handling ─  all of which are automatically customized to the user’s individual configuration. This level of testing is critical to ensure that IP components will function in all of the intended SoC applications.  The Accelerated VIP gives a 100x boost in simulation throughput of Universal Verification Methodology (UVM)-compliant testbenches using the Cadence Palladium XP verification computing platform.  This simulation-acceleration usage mode lets users perform full-chip simulation that would otherwise be impossible or impractical in RTL simulation alone.

“The Cadence PCIe VIP is a broad, highly differentiated, and proven solution with distinct customer advantages for PCI Express verification,” said Erik Panu, vice president of R&D, SoC Realization Group at Cadence.  “No other VIP solution provides users all the capabilities found in the Cadence offering including more than 40 interface protocols and over 6,000 memory models that have been deployed in thousands of designs.”

According to A. Vasudevan, vice president, Semiconductor and Systems at Wipro, “We have been consistently enabling semiconductor companies to reduce verification time and increase coverage parameters through next generation frameworks and market proven end-to-end verification services. Our partnership with Cadence has played an instrumental role in fulfilling the IP verification needs of our customers. We chose PCIe 3.0 VIP, along with TripleCheck, to achieve a comprehensive solution that gives us the fastest path to IP verification closure.”

More information about the Cadence PCI Express Verification IP at www.cadence.com/products/fv/verification_ip/Pages/pci_express.aspx

Technical papers     

• AR RF/Microwave Instrumentation Field Analyzers
• 16-Bit, 100 kSPS Low Power Successive Approximation ADC System
• Replacing the Candle in the Candelabra
• Adaptive Cell Converter Topology Enables Constant Efficiency in PFC Applications

December 15, 2011 | Texas instruments | 222901974

Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.