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Cadence adds new capabilities to PCIe VIP including PIPE4 support to boost performance

July 12, 2012 // Paul Buckley

Cadence adds new capabilities to PCIe VIP including PIPE4 support to boost performance

Cadence Design Systems, Inc. has released new capabilities in its PCI Express Verification IP (PCIe VIP) which result in more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels.


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The Cadence technology includes support for the new PCIe PIPE4 specification; new performance measurement features critical for optimizing PCIe implementation; TripleCheck test suite, coverage and verification plan to shorten and ease testing for full PCIe specification compliance; and Accelerated PCIe VIP that drives the verification speed required for large SoCs.

The release addresses the full spectrum of PCIe applications and supports the latest specifications, including SR-IOV, MR-IOV, NVMe and PIPE4, empowering customers to implement designs quickly and confidently incorporating the newest PCI Express interfaces.

Already used on hundreds of production designs, the Cadence PCIe VIP enables efficient and thorough verification of SoCs. A new performance measurement utility helps customers optimize their designs for improved link utilization, throughput, latency, and power. The PCIe TripleCheck IP Validator, Cadences third-generation compliance solution, verifies that IP blocks comply fully with protocol specifications. TripleCheck combines the three most critical components of verification in a single, easy-to-use environment: a test suite, coverage model, and verification plan covering all sections of the PCIe specification including PL, DLL, TL, Power Management and Error Handling all of which are automatically customized to the users individual configuration. This level of testing is critical to ensure that IP components will function in all of the intended SoC applications. The Accelerated VIP gives a 100x boost in simulation throughput of Universal Verification Methodology (UVM)-compliant testbenches using the Cadence Palladium XP verification computing platform. This simulation-acceleration usage mode lets users perform full-chip simulation that would otherwise be impossible or impractical in RTL simulation alone.
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