Under the agreement, the companies will develop double data rate memory
PHY cores, memory controllers, and protocols such as PCIe and Ethernet
for use on 32-nanometer silicon-on-insulator manufacturing processes.
The technology will be used in servers, video games and other devices.

"Qualifying and integrating complex IP is a costly and growing burden
for many of our customers," said Vishal Kapoor, vice president of
product management at Cadence, in a statement. "We look forward to
teaming with IBM to relieve some of that burden for engineering teams
as they grapple with SoCs and systems that will only continue to grow
in size and complexity."

"The IP we're working on with Cadence will provide state-of-the-art
building blocks that will allow our customers to build more powerful,
higher bandwidth networking and communications technology," said Marie
Angelopoulos, a director with IBM Microelectronics, in the same
statement.