Cadence Encounter digital technology delivers 29 percent power reduction on 'green' network flow processor SoCs
May 14, 2012 // Paul Buckley
Netronome, a developer of intelligent network flow processors (NFP), has gained a performance advantage on the company's low-power 'green' SoCs by using the Cadence Encounter RTL-to-GDSII flow.
In addition to increased chip performance, Netronome engineers using the latest Encounter 11.1 technology achieved a 29% reduction in power consumption, smaller design area and faster overall time to market compared to their former flow, for SoCs targeting the secure virtualized cloud and data center markets. The Cadence En counter RTL-to-GDSII flow - including RTL Compiler, the Encounter Digital Implementation System, and Encounter Test - helps design teams optimize power, performance, and area for the world's most advanced high-performance, low-power SoC designs.
Netronome's OEM customers have constraints on power budgets, which required the company to optimize its high-performance 40Gbps NFPs for low-power consumption for use in their customers' switches, routers, load balancers and cyber-security platforms. Netronome engineers were tasked with improving chip power efficiencies across multi-mode, multi-corner and on-chip variation scenarios. Implementing robust clock trees that consume less dynamic switching and static leakage power without compromising on performance was difficult under such extreme requirements. Furthermore, as chip power consumption increases, it costs more to design, fabricate, operate and cool devices and systems.
“Using the complete Cadence Encounter RTL-to-GDSII flow, we were able to tape out a complex 1.4 GHz 40-core micro-engine-based Network Flow Processor on schedule, achieving a 29 percent power savings and 10 percent improvement in timing,” said Jim Finnegan, senior vice president, Silicon Engineering at Netronome. “We were particularly impressed with the newly integrated Clock Concurrent Optimization ( CCOpt ) technology in the Encounter flow and its unique ability to optimize clocks and data-path simultaneously allowing us to eliminate several manual design steps and achieve superior performance, power and area results on our design. This gives us a competitive advantage in our end market.”
Clocks are the backbone of all digital chips, and a fundamentally different approach to clock construction and optimization was needed. Traditional clock tree synthesis (CTS) tools and methodologies - which are based on minimizing skew and are isolated from logic/physical optimization - are insufficient for advanced node, high-performance designs due to the growing gap between pre- and post-CTS design timing. CCOpt technology bridges the gap by re-focusing CTS directly on timing - not skew minimization - and combining this timing-driven CTS with concurrent logic/physical optimization.
“Network Flow processing chips are tough to design. They're big, they're fast, and they have to minimize power consumption. It is conditions like these where the Encounter RTL-to-GDSII flow really shines,” said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence.
Visit Cadence at www.cadence.com
European BLIM4SME project aims to further streamline Bluetooth Low Energy integration
December 12, 2013
Initiated by RivieraWaves and CSEM, the European funded BLIM4SME project will develop miniature wireless modules targeting ...
Additive photolithographic process yields micro flex circuits with 5µm feature resolution
Flexible haptics and capacitive touch combo solution enables more intuitive interfaces
Bosch suggests cars to coast for fuel efficiency
Europe is giving up on leading edge digital chip design
Design-free RF-based wireless charging redefines user experience
December 11, 2013
Although it was established in July 2010, funded by private investors, Israeli startup Humavox has been operating pretty ...
Electromobility, Formula One and the Fatal Consequences of Bad Software Design: The top ten stories of 2013
Brushless DC servo motors integrate field-oriented closed-loop servo control
How green is your code?
- UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing
- Managing Electrical Complexity with a Platform Level Approach and Systems Engineering
- 3mm × 3mm QFN IC Directly Monitors 0V to 80V Supplies
- Adaptive Cell Converter Topology Enables Constant Efficiency in PFC Applications
InterviewPerformance monitoring solution helps provide intelligent control of high power systems
A performance monitoring solution designed to enable companies to monitor high power IGBT module systems in locomotive, wind turbine, High Voltage DC and industrial drive applications was unveiled this ...
Filter WizardCheck out the Filter Wizard Series of articles by Filter Guru Kendall Castor-Perry which provide invaluable practical Analog Design guidelines.
Linear video channel
READER OFFERRead more
Internet of Things (IoT) manufacturer Ciseco has launched the Raspberry Pi ‘Wireless Inventors Kit’ (RasWIK), featuring 88 pieces to provide everything a Pi owner needs to follow a series of step-by-step projects or to create their own wireless devices, without the need for configuration or even writing code.
RasWIK has been designed to be highly accessible, demystifying the dark art of wireless and enabling anyone with basic computing skills to begin building wireless devices with a Raspberry Pi. You can create anything from a simple traffic light, to a battery monitor, or even a temperature gauge that sends data to the Xively IoT cloud so billions can access the data.This month, Ciseco is giving away twelve Raspberry Pi Wireless Inventors kits, worth £49.99 each for EETimes Europe's readers to win.
And the winners are...
In our previous reader offer, Farsens was giving away five kits for EEtimes Europe readers to evaluate its FenixVortex, Kineo and X1 wireless, battery free sensor tags.
Lucky winners include Mr A. Neil from the UK, Mr. E. Delvaux from Belgium, Mr Lengal from the Czech Republic, Mr H. Bijlsma from the Netherlands, and Mr G. Pfaff from Germany. All should be receiving their packages soon. Lets wish them some interesting findings with their projects.
December 15, 2011 | Texas instruments | 222901974
Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.