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Cadence updates design flow for 'end-to-end silicon realisation'

January 31, 2011 // Phil Ling

Cadence updates design flow for 'end-to-end silicon realisation'

With the cost of developing an integrated device on a 28nm process expected to be in the region of $100million, Cadence is turning its focus on improving the design flow and reducing the cost of development through Silicon Realization, part of the company's EDA360 initiative.

The latest move in this direction is a proven end-to-end flow for 28nm design that brings together a range of the company's point-tools to enable a simpler approach to developing devices that run at GHz and/or have in excess of 100 million transistors.

This 'Giga gate/GHZ' flow is expected to be applicable to any design that prioritises low power or has mixed signal elements, in other words all new IC designs.

Cadence believes that, while not all IDMs will be developing at 28nm today, within 3 years most will. With its unique challenges, such as double-patterning, 28nm design will demand more from today's point-tools; the new end-to-end flow is intended to deliver the extra level of integration to eliminate design iteration, one of the key causes of extended development cycles.

An important part of the overall philosophy is encapsulated by the company's vision of a unified design, implementation and verification flow based on intent, abstraction and convergence; three tags that are likely to feature strongly in the EDA360 initiative.

This extends to leading-edge designs that hope to take advantage of 3D-IC using silicon interposers – which analysts believe will become more significant in the next few years – as the flow will also cover package design.

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