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CEA-Leti ramps up 300-mm 3-D fab

January 18, 2011 // Peter Clarke

CEA-Leti ramps up 300-mm 3-D fab

France's CEA-Leti research center in Grenoble has begun to ramp up production on its 300-mm wafer fabrication facility dedicated to 3D-integration applications.

By adding this technology to its existing 300-mm CMOS R&D line, Leti now can offer heterogeneous integration technologies to customers on both 200- and 300-mm diameter wafers.

The line has cost about 15 to 18 million euro (about $18 to $24 million) according to Andre Rouzaud, deputy vice president in microsystems and integration. Rouzaud stressed that it would cost considerably more to set up a commercial 3-D line as Leti has been able to recycle some equipment and has other equipment placed with it as part of research cooperation with partner companies.

The line is dedicated to R&D and prototyping and can provide 3-D oriented lithography, deep etching, dielectric deposition, metallization, wet etching and packaging tools that will be available for Leti's partner and customers.

There is no figure of merit for manufacturing throughput of the line. "We're not focused on throughput but on development and developing processes. Tools are constantly being reconfigured" said Mark Scannell, program manager for 3-D integration. However, it was stressed that the processes that are being developed at CEA-Leti are being done so with commercial throughput in mind.

Leti claims to have a large portfolio of through-silicon vias (TSVs) as well as capabilities in alignment, bonding, thinning, and interconnects in specific integration schemes for manufacturing optimized die stacks.

CEA-Leti is known to be a close partner of STMicroelectronics and plans to work with Shinko Electric Industries Co. Ltd. (Nagano, Japan) a developer of silicon interposer substrates, Scannell said. "In very high-end research there are some confidential prototypes," he added saying the names could not be shared at this time.

The stacking of die in multichip packages has been happening for some time through the use of bond wires on simple stepped stacks. However the use of TSVs is expected to have a major impact on design density. TSVs are also in commercial operation for some simple operations. Xilinx has used TSVs to attach four FPGA die to a substrate. Similarly TSVs have been used for back side attach to image sensors. However, there is still a lot of research and optimization to be done said Scannell.

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