Challenges and Solutions for Future Main Memory
May 26, 2010 // Rambus // 0 comments
Download White Paper 1Mo
This whitepaper presents an architectural concept for a future memory system that addresses the anticipated demand for higher bandwidth with higher data rates, lower power, higher throughput and higher capacity. The future memory architectural concept, employing Rambus innovations, doubles data rates over current DDR3 memory and substantially improves throughput and transfer efficiency with 64Byte accesses. The architecture reduces standby, IO and core power, and can natively support higher capacities per memory channel.
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READER OFFER
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The SoCKIT evaluation kit is Arrow's latest development tool, featuring an Altera Cyclone V SoC with a dual-core ARM Cortex-A9 MPCore processor integrated within its 28nm FPGA fabric.
Altera SoCs allow embedded system developers to differentiate their end product with customized hardware and software, and extend the product lifecycle through hardware and software updates in the field. This month, Arrow Electronics is giving away five SoCKIT evaluation kits featuring Altera’s ARM-Based SoCs, worth €249 each, together with the free entrance to one of Arrow’s SoC workshops organized throughout Europe.
And the winners are...
In our previous reader offer, Freescale Semiconductor was giving away five IMX6Q, Sabre-lite kits, worth £128.06 each.
Lucky winners include Mr. X. Salada Sole from the UK, Mrs A. Peric from Germany, Mr Z. Janosy from Hungary, Mr D. Gacina from Croatia and Mr B. Boris from France. All should be receiving their packages soon. Let's wish them some interesting findings with their projects.
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