Challenges and Solutions for Future Main Memory
May 26, 2010 // Rambus // 0 commentsDownload White Paper 1Mo
This whitepaper presents an architectural concept for a future memory system that addresses the anticipated demand for higher bandwidth with higher data rates, lower power, higher throughput and higher capacity. The future memory architectural concept, employing Rambus innovations, doubles data rates over current DDR3 memory and substantially improves throughput and transfer efficiency with 64Byte accesses. The architecture reduces standby, IO and core power, and can natively support higher capacities per memory channel.
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