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Challenges and Solutions for Future Main Memory

May 26, 2010 // Rambus // 0 comments

Challenges and Solutions for Future Main Memory Download White Paper 1Mo

This whitepaper presents an architectural concept for a future memory system that addresses the anticipated demand for higher bandwidth with higher data rates, lower power, higher throughput and higher capacity. The future memory architectural concept, employing Rambus innovations, doubles data rates over current DDR3 memory and substantially improves throughput and transfer efficiency with 64Byte accesses. The architecture reduces standby, IO and core power, and can natively support higher capacities per memory channel.


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This month Ambiq Micro is giving away five of its 'Apollo EVB' evaluation boards, worth 9 each for EETimes Europe’s readers to assess the capabilities of their cutting-edge Apollo sub-threshold microcontroller.

The new suite of Apollo MCUs is based on the 32-bit ARM Cortex-M4 floating point microcontroller and redefines 'low power' with energy consumption that is typically five to ten times lower than that of MCUs of comparable performance (thanks to Ambiq’s patented Subthreshold Power Optimized Technology platform).


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