Design Optimization and Analysis of IC Packages for USB 3.0
February 16, 2011 // Mentor Graphics // 0 commentsDownload White Paper 1Mo
USB 3.0 is rapidly being adopted by a growing number of system level companies, spawning many integrated device manufacturers (IDMs) to develop new chips to address this need. USB 3.0 supports data transfer rates up to 4.2 Gbits/sec, creating new challenges for IC package designers and signal integrity engineers that must be addressed as part of the high-speed SERDES design process. This paper will introduce important design considerations and an effective high-speed design methodology recently successfully employed for the design of a commercial USB 3.0 part.
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