Design platform accelerates the delivery of compute-intensive algorithms for SoCs
May 16, 2012 // Julien Happich
Esencia Technologies has launched the EScala design platform, claimed to drastically reduce the development time required to implement complex, compute-intensive algorithms on a SoC from months to only days.
According to the company, algorithms that would months to architect, design and verify in RTL can be implemented on an EScala design platform in weeks. EScala uses C/C++ as a design entry language and automatically generates an application-specific programmable core. With EScala, the designer is able to optimize and scale the generated core to best fit the application's area, low power and performance profile. EScala targets algorithms that are currently too demanding to efficiently run on traditional CPUs, like ARM’s Cortex-M or Cortex-R series. A single EScala core offers computational performance that is up to 32 times higher than traditional RISC cores. Additionally the design platform offers built-in support for multi-core architectures that can take on even the most MIPS-hungry algorithms. Many high-end algorithms have very unique memory bandwidth requirements.
EScala supports fully scalable memory interfaces that enable system architects to prevent their cores from being memory bandwidth limited. Migrating algorithms to EScala is easy. The EScala design platform comes with a full software development environment (SDK) for C and C++ that includes an integrated debugger and simulator. Programmers are not forced to use CPU-specific intrinsics or special libraries to get good performance results. The EScala compiler will take care of optimizations. This is a result of Esencia’s proprietary patent pending optimization technology that is used to generate the cores, as well as its run-time code. The EScala design platform generates synthesizable RTL code and related scripts to easily integrate it into an ASIC SoCs. It supports standard bus protocols interfaces like AMBA AHB/AXI as well as Wishbone. These interfaces make it easy to integrate EScala cores with the wide variety of available peripheral IPs. To connect tightly coupled high speed RAM, optimized memory interface protocols are available.
Visit Esencia Technologies at www.esenciatech.comAll news
Big moves in chip vendor top 20 ranking
December 10, 2013
IHS has produced a ranking of the top 20 chip vendors by projected sales in 2013 that shows memory chip vendor Micron Technologies ...
Extendible processors go head to head backed by EDA giants
Koch Industries acquires Molex for USD7.2 billion
EnOcean joins the OSGi Alliance to define universal open interface for energy harvesting wireless
GaN-on-silicon LEDs to grow market share to 40 percent by 2020
Pebble CEO turns back clock
December 09, 2013
The night before Eric Migicovsky opened a door to what would become a $10 million windfall, he was sitting in his living ...
Tyndall National Institute captures snapshots of moving atoms under bursts of light
Measurement technique allows survey of 3D micro objects
The Top 10 Most Popular Power Management Technical Articles of 2013
- 3mm × 3mm QFN IC Directly Monitors 0V to 80V Supplies
- UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing
- Adaptive Cell Converter Topology Enables Constant Efficiency in PFC Applications
- Isolated 4-Channel, Thermocouple/RTD Temperature Measurement System with 0.5°C Accuracy
InterviewPerformance monitoring solution helps provide intelligent control of high power systems
A performance monitoring solution designed to enable companies to monitor high power IGBT module systems in locomotive, wind turbine, High Voltage DC and industrial drive applications was unveiled this ...
Filter WizardCheck out the Filter Wizard Series of articles by Filter Guru Kendall Castor-Perry which provide invaluable practical Analog Design guidelines.
Linear video channel
READER OFFERRead more
Internet of Things (IoT) manufacturer Ciseco has launched the Raspberry Pi ‘Wireless Inventors Kit’ (RasWIK), featuring 88 pieces to provide everything a Pi owner needs to follow a series of step-by-step projects or to create their own wireless devices, without the need for configuration or even writing code.
RasWIK has been designed to be highly accessible, demystifying the dark art of wireless and enabling anyone with basic computing skills to begin building wireless devices with a Raspberry Pi. You can create anything from a simple traffic light, to a battery monitor, or even a temperature gauge that sends data to the Xively IoT cloud so billions can access the data.This month, Ciseco is giving away twelve Raspberry Pi Wireless Inventors kits, worth £49.99 each for EETimes Europe's readers to win.
And the winners are...
In our previous reader offer, Farsens was giving away five kits for EEtimes Europe readers to evaluate its FenixVortex, Kineo and X1 wireless, battery free sensor tags.
Lucky winners include Mr A. Neil from the UK, Mr. E. Delvaux from Belgium, Mr Lengal from the Czech Republic, Mr H. Bijlsma from the Netherlands, and Mr G. Pfaff from Germany. All should be receiving their packages soon. Lets wish them some interesting findings with their projects.
December 15, 2011 | Texas instruments | 222901974
Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.