DesignWare embedded memories and logic libraries for TSMC 28-nanometer processes
This balance is especially critical in mobile applications. In combination with the embedded test and repair technology of the DesignWare STAR Memory System, Synopsys’ embedded memories and standard cell libraries offer designers an advanced, comprehensive IP solution for creating high performance, low-power 28nm SoCs with reduced test and manufacturing costs. DesignWare 28nm Logic Libraries take advantage of multiple threshold variants and gate length bias combinations to deliver optimal performance and power results for a wide variety of SoC applications. These libraries offer multiple, synthesis-friendly cell sets and router-friendly standard cell library architectures designed for multi-GHz performance with minimal die area and high manufacturing yield.
Power Optimisation Kits (POKs) provide designers with advanced power management capabilities supported by popular low-power design flows, including shut-down, multi-voltage and dynamic voltage frequency scaling (DVFS). For power-sensitive applications such as mobile devices, all of Synopsys’ 28nm memories incorporate source biasing and multiple power management modes that significantly reduce leakage and dynamic power dissipation. Synopsys’ ultra high-density two-port SRAM and 16 Mbit single-port SRAM compilers further reduce area and leakage by up to 40% compared to standard high-density memories, enabling SoC developers to implement memories with a differentiated blend of high performance, small area and extremely low power.
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