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DSP dumps external memory bus in favour of lower cost

September 14, 2010 // Philip Ling

DSP dumps external memory bus in favour of lower cost

By reducing the on-chip program memory, adding factory-coded ROM and removing the external memory bus, Analog Devices has slashed the price of its latest Blackfin DSP to just USD3. The BF592 implements the same dual-MAC core to deliver 800 MMACS at 400 MHz, but delivers it at the company's lowest ever volume price point.


The company claims the new device costs around 40% less than its next nearest Blackfin device.

The latest Blackfin member is the first to implement a L1 cache that uses a combination of RAM and factory-coded ROM. By pre-loading the 64K instruction ROM with the company's VDK real-time operating system and C runtime libraries, it significantly reduces the amount of SRAM needed. By removing the external memory bus, the number of pins on the device is also slashed from over 200 to just 64. Together, these innovative developments have helped bring down the price while maintaining raw DSP performance. Software compatibility is also maintained with all other BF5xx-based devices.

The BF592 is also the lowest power device in ADI's Blackfin portfolio, consuming as much as 80% less power than the closest Blackfin alternative. The company hopes this will make it viable for a range of low cost, low power consumer devices, as well as automotive applications; the BF592 will be available in automotive grade from launch. While the company claims it will see some design wins in the automotive sector, it maintains it isn't the lead market for the BF592.

With no external memory bus and limited on-chip non-volatile program storage, the BF492 is able to boot from an external memory via a variety of serial interfaces. The high DSP performance coupled with limited program space – 32kbyte instruction SRAM and 32kbyte data SRAM – indicates the BF592 will be used as a co-processor in applications where bursts of signal processing activity are required. Tightly coded algorithms using the on-chip C runtime libraries will likely be best placed to make full use of the potential 800 MMACs.

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