Dual channel 6 Gb/s SERDES with low-noise clock synthesizer targets next generation radio
December 01, 2010 // Jean-Pierre Joosting
PMC-Sierra has announced its SynthePHY™ family of integrated dual channel 6 Gb/s SERDES and programmable clock synthesizer solutions optimized for wireless infrastructure radio designs.
The SynthePHY products offer 30 clock outputs that can be programmed over a wide frequency band, ranging from 3 MHz to 1.6 GHz and meet the phase noise performance required by multi-carrier GSM, WCDMA and LTE systems.
“Wireless infrastructure OEMs are under tremendous pressure to lower their development costs by reducing the number of RF product variants,” said Tom Sun, Vice-President and General Manager for PMC-Sierra’s Broadband Wireless Division. “Our SynthePHY family is highly programmable and designed to meet the rigorous phase noise performance and wideband support required for next generation multi-standard radio platform designs.”
With each new generation of equipment, base station radios are required to provide more functionality, with lower power, in the same form-factor. The SynthePHY replaces up to four components by integrating dual 6 Gb/s SERDES, jitter cleaner, on-chip voltage controlled oscillator, clock synthesizer and 30 programmable clock drivers (see Figure 1). It requires only 2200 mW to operate all functions at their maximum rates. The high integration and low power of device make it suitable for rack-mounted radios, as well as remote radio units where size and power are highly constrained.
SynthePHY integrates PMC-Sierra’s robust SERDES technology to support CPRI, OBSAI, and IR remote radio unit (RRU) designs. The SERDES rates are programmable from 614.4 Mbps to 6.144 Gbps data rates and are suitable for driving cable, backplane or optical modules making it possible to share a common radio design for rack-mount and remote radios. SynthePHY includes the accurate delay calibration circuitry needed for measuring delays to satisfy CPRI and OBSAI synchronization requirements. This feature reduces the effort required to develop calibration circuits and provides the accuracy needed for multi-hop remote radio systems.
SynthePHY has 18 differential low voltage 50-ohm drivers with programmable output levels and phase control, and supports clock rates up to 1.6 GHz. In addition, each device has 12 single-ended LVCMOS drivers with programmable divider and phase control, and supports clock rates up to 307.2 MHz. Integrated jitter of less than 200 fs and phase noise floor below -160 dBc/Hz on 1 GHz differential output clocks and 250 MHz LVCMOS output clocks can be achieved using a low-cost VCXO reference. The high number of flexible outputs and low-noise characteristic of SynthePHY enables scaling from single sector designs to multi-sector, multi-standard, and MIMO designs.
The SynthePHY family includes the PM7501 SynthePHY 6G and PM7520 SyntheCLK devices.
The PM7501 SynthePHY 6G features: dual 6Gb/s SERDES, 18 differential and 12 LVCMOS outputs, and comes in a 3- x 13-mm body, 225-lead, 0.8-mm pitch flip chip CSP (fcCSP).
The PM7520 SyntheCLK features: 18 differential and 12 LVCMOS outputs, and comes in a 12- x- 12-mm body, 196-lead, 0.8-mm pitch flip chip CSP (fcCSP).
The devices are rated for industrial temperature operation (-40 to +85 °C). A comprehensive support package, including datasheets, application notes and reference design material is available at: www.pmc-sierra.com/MyPMC.
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