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Dual channel 6 Gb/s SERDES with low-noise clock synthesizer targets next generation radio

December 01, 2010 // Jean-Pierre Joosting

Dual channel 6 Gb/s SERDES with low-noise clock synthesizer targets next generation radio

PMC-Sierra has announced its SynthePHY™ family of integrated dual channel 6 Gb/s SERDES and programmable clock synthesizer solutions optimized for wireless infrastructure radio designs.

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The SynthePHY products offer 30 clock outputs that can be programmed over a wide frequency band, ranging from 3 MHz to 1.6 GHz and meet the phase noise performance required by multi-carrier GSM, WCDMA and LTE systems.

Wireless infrastructure OEMs are under tremendous pressure to lower their development costs by reducing the number of RF product variants, said Tom Sun, Vice-President and General Manager for PMC-Sierras Broadband Wireless Division. Our SynthePHY family is highly programmable and designed to meet the rigorous phase noise performance and wideband support required for next generation multi-standard radio platform designs.

With each new generation of equipment, base station radios are required to provide more functionality, with lower power, in the same form-factor. The SynthePHY replaces up to four components by integrating dual 6 Gb/s SERDES, jitter cleaner, on-chip voltage controlled oscillator, clock synthesizer and 30 programmable clock drivers (see Figure 1). It requires only 2200 mW to operate all functions at their maximum rates. The high integration and low power of device make it suitable for rack-mounted radios, as well as remote radio units where size and power are highly constrained.

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