Dual channel 6 Gb/s SERDES with low-noise clock synthesizer targets next generation radio
December 01, 2010 // Jean-Pierre Joosting
PMC-Sierra has announced its SynthePHYô family of integrated dual channel 6 Gb/s SERDES and programmable clock synthesizer solutions optimized for wireless infrastructure radio designs.
Wireless infrastructure OEMs are under tremendous pressure to lower their development costs by reducing the number of RF product variants, said Tom Sun, Vice-President and General Manager for PMC-Sierras Broadband Wireless Division. Our SynthePHY family is highly programmable and designed to meet the rigorous phase noise performance and wideband support required for next generation multi-standard radio platform designs.
With each new generation of equipment, base station radios are required to provide more functionality, with lower power, in the same form-factor. The SynthePHY replaces up to four components by integrating dual 6 Gb/s SERDES, jitter cleaner, on-chip voltage controlled oscillator, clock synthesizer and 30 programmable clock drivers (see Figure 1). It requires only 2200 mW to operate all functions at their maximum rates. The high integration and low power of device make it suitable for rack-mounted radios, as well as remote radio units where size and power are highly constrained.
SynthePHY integrates PMC-Sierras robust SERDES technology to support CPRI, OBSAI, and IR remote radio unit (RRU) designs. The SERDES rates are programmable from 614.4 Mbps to 6.144 Gbps data rates and are suitable for driving cable, backplane or optical modules making it possible to share a common radio design for rack-mount and remote radios. SynthePHY includes the accurate delay calibration circuitry needed for measuring delays to satisfy CPRI and OBSAI synchronization requirements. This feature reduces the effort required to develop calibration circuits and provides the accuracy needed for multi-hop remote radio systems.All news
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