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EDA tool optimises cell libraries for processor cores in SoCs

June 13, 2013 // Graham Prophet

EDA tool optimises cell libraries for processor cores in SoCs

Synopsys has announced a physical-IP design kit optimised for SoC processor cores; the DesignWare HPC Design Kit yields superior performance, power and area for CPU, GPU and DSP Cores


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Synopsys has announced an extension to its DesignWare Duet Embedded Memory and Logic Library IP portfolio specifically designed to enable the optimised implementation of a broad range of processor cores. The new DesignWare HPC (High Performance Core) Design Kit contains a suite of high speed and high density memory instances and standard cell libraries that allow system on chip (SoC) designers to optimise their on chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power or to achieve an optimum balance of the three for their specific application. Synopsys developed in collaboration with partners including Imagination Technologies, CEVA and VeriSilicon.

The tool operates in conjunction with the synthesis stage of a design flow (in a flow where the synthesis is aware of floorplanning issues), and is in part empirical; based on studies of what works best when implementing logic structures typical of processor cores, it selects and lays down specific standard cell variants when it recognises certain features of processor logic, improving speed, power and silicon area. It includes around 125 new cells and memory elements. Initially focused on TSMC's 28-nm HPM process, Synopsys says it will produce variants for other processes at that node, including low-power versions; 16-nm fin-FET processes are a further possible target, and the company may look back at 40-nm processes if demand exists. The optimisation package uses standard Liberty syntax.

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