Print  |  Send  |   

Error Correction Code in SoC FPGA-Based Memory Systems

April 11, 2012 // Hans Spanjaart, Matthew Prather, Altera // 0 comments

Error Correction Code in SoC FPGA-Based Memory Systems Download White Paper 361Ko

Gone are the early days of embedded design when a few kilobytes of static RAM was all that was needed. Today's applications reap the benefits of integration and functionality, but leave challenges once reserved for high-performance computing such as soft errors. As the memory in embedded systems grows, you will need to pay more attention to soft errors. Discover why mitigating soft errors through error correction code (ECC) can improve your embedded designs. Understand the potential sources and implications of soft errors and learn how Altera designed its SoC FPGA products to greatly improve resilience of systems against soft errors.


All White Papers


Submit a white paper

Follow us

Fast, Accurate & Relevant for Design Engineers only!

Technical papers     

Linear video channel

READER OFFER

Read more

This month, DecaWave is offering EETimes Europe's readers the chance to win two TREK1000 kits to evaluate its Ultra-Wideband (UWB) indoor location and communication DW1000 chip in different real-time location system topologies.

Worth €947, the kit allow designers to prove a concept within hours and have a prototype ready in days. Based on the two-way ranging scheme, the kit lets you test three different topologies.

MORE INFO AND LAST MONTH' WINNERS...

Design centers     

Automotive
Infotainment Making HDTV in the car reliable and secure

December 15, 2011 | Texas instruments | 222901974

Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.

 

You must be logged in to view this page

Login here :