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Error Correction Code in SoC FPGA-Based Memory Systems

April 11, 2012 // Hans Spanjaart, Matthew Prather, Altera // 0 comments

Error Correction Code in SoC FPGA-Based Memory Systems Download White Paper 361Ko

Gone are the early days of embedded design when a few kilobytes of static RAM was all that was needed. Today's applications reap the benefits of integration and functionality, but leave challenges once reserved for high-performance computing such as soft errors. As the memory in embedded systems grows, you will need to pay more attention to soft errors. Discover why mitigating soft errors through error correction code (ECC) can improve your embedded designs. Understand the potential sources and implications of soft errors and learn how Altera designed its SoC FPGA products to greatly improve resilience of systems against soft errors.


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This month, Arrow Electronics is giving away ten BeMicro Max 10 FPGA evaluation boards together with an integrated USB-Blaster, each package being worth 90 Euros, for EETimes Europe's readers to win.

Designed to get you started with using an FPGA, the BeMicro Max 10 adopts Altera's non-volatile MAX 10 FPGA built on 55-nm flash process.

The MAX 10 FPGAs are claimed to revolutionize non-volatile integration by delivering advanced processing capabilities in a low-cost, instant-on, small form factor programmable logic device.

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