PARIS — Europe has an opportunity to revitalize its EDA and chip sectors as deep sub-micron manufacturing introduces such challenges as transistor wear-out and process and design variability, according to participants in collaborative research programs such as MEDEA+.

Even though leading European chip companies are preparing to build their chips on CMOS processes provided by foundries after the 45-nm node, in the design-for-manufacturing era even fabless chip companies must be manufacturing savvy if their designs are going to work.

The biggest opportunity may be in EDA. A major change is needed at the system-level design phase, speakers agreed at the MEDEA+ Design Automation Conference held recently in Grenoble, France. The inclusion of design in this year's MEDEA+ conference highlights that it can no longer be kept separate from manufacturing. The EDA industry is being called upon to provide tools that predict the yield, reliability and power consumption of ICs early in the design flow.

"The challenges for circuit design based on 45-nm, 32-nm technologies and below cannot be managed with the methodologies used for current state-of-the art technologies, commented Andreas Ripp, vice president of sales and marketing at MunEDA GmbH (Munich, Germany). "Based on the molecular and atomic structures of these manufacturing processes, the circuit design and sizing have to be seen as a problem because of statistical variations and distributions of electrical and geometrical parameters. Most of these effects are analog effects that now affect digital structures. Most companies observe that working with process corners is no longer a sufficient way to design their circuits and therefore need sophisticated tools for analysis and optimization of statistical parameters in their designs.

Guaranteeing the conventional ten-year life of ICs is going to become increasingly difficult, asserted Antonis Papanikolaou from the Interuniversity Microelectronics Centre (IMEC) in Leuven, Belgium. This results from the combination of feature dimension miniaturization, the introduction of novel materials and the saturation of supply voltage scaling. "We will see wear-out mechanisms with new properties in the future. The progressive degradation of the electrical characteristics of transistors and wires will start dominating over abrupt functional failures. Furthermore, the mean-time-to-first-soft-break will significantly diminish, he continued.

Among the wear-out mechanisms is charge trapping in the semiconductor channel. While that also happens in larger transistors the effect on the millions of electrons flowing is usually insignificant. As the channel size and the number of electrons reduces the charge trapping starts to have an effect on threshold voltage and degrades performance.

Papanikolaou explained that the industry would have to cope with design and testing challenges in parallel, as conventional testing techniques can only capture problems during manufacturing. "Aggressive burn-in techniques to capture weak devices may lead to excessive manufacturing yield loss, while ignoring time-dependent variability during testing will lead to expensive field returns, he commented.

The progress of Moore's law means that transistor wear-out and statistical performance issues are beginning to cross over from the realms of academic and hypothetical discussion to real-world R&D engineering.

At the conference Philippe Magarshack, vice president of central R&D at STMicroelectronics NV (Geneva, Switzerland), acknowledged this and called for stronger links between academia, SMEs, EDA vendors, system houses, as well as the IC design and manufacturing community. "It is only with a holistic approach encompassing process, device modeling, reliability, lithography, memory designers, I/O designers, power switch experts, that the full capabilities of 45 nm and beyond will be unleashed, he declared.

Recent signs indicate that Europe intends to get its teeth into process variability and reliability challenges to retain a seat at the top table in the semiconductor industry, whether in a fabless or manufacturing role.

Europe is indeed host to a number of research programs on analog, mathematical and physical effects, and Ripp said solutions and methodologies coming from Europe are ahead of the game in the battle against these problems.

Within a three-year MEDEA+ project, dubbed HONEY (Highly Optimized DesigN MEthods for Yield and Reliability) and launched in January 2007, a European consortium of industrial semiconductor and EDA companies including STMicroelectronics, Infineon Technologies AG, X-Fab Semiconductor Foundries AG, Xyalis and MunEDA is working on ways to improve yield and reliability without affecting the silicon process.

Other European EDA research projects adopted by MEDEA+ and referenced by Ripp include PARACHUTE, NanoTEST, ROBIN and LoMoSa+ intended to strengthen Europe's technology advantages in specific areas such as analog, nonvolatile memory, RF communications and automotive electronics.

Papanikolaou also highlighted IMEC's Technology Aware Design research program, whose initial aim is to analyze the impact of time-dependent variability on the system-level performance metrics and lifetimes of embedded systems.

In a second phase, IMEC plans to exploit the gradual nature of the wear-out mechanisms to try and develop self-adaptive circuits. In this context, Papanikolaou noted that IMEC is a partner in two proposals submitted to the European Union, namely LOTUS and REALITY. While the former focuses on the analysis of reliability wear-out effects at all levels of process technology, the latter aims to analyze their impact at all levels of the design process and to provide design tools able to exploit this understanding.

Ripp said he believes it is important for the European industry and community to enlarge existing funding initiatives and directly promote the foundation and growth strategies for European EDA startups and spinoffs from research institutes. "Europe should invest to establish a strong European EDA industry that would deliver software for European technology leaders and face the competition of today's U.S.-dominated EDA industry, Ripp concluded.