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High speed data converter simplifies FPGA interconnect design

October 08, 2012 // Nick Flaherty

High speed data converter simplifies FPGA interconnect design

Analog Devices has launched a dual-channel, 14bit, 250MSPS, analog-to-digital converter that connects seamlessly to high-speed FPGAs and enables precise multi-channel converter synchronisation.


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The AD9250 features a JEDEC JESD204B serial output data interface standard and is first-to-market with full JESD204B Subclass 1 deterministic latency at 250MSPS. This accommodates the precise synchronisation of multiple data-conversion channels through a serial interface.
Communications infrastructure, imaging equipment, industrial instrumentation, defence electronics and other multi-channel, data-hungry systems are demanding wider resolutions and higher sampling rates from the data conversion stage. Physical layout constraints of the parallel interface and bit-rate limitations of the serial LVDS (low-voltage differential signalling) approach are beginning to present technical barriers for designers. The JESD204B serial interface reduces the number of high-speed differential output data paths required from as many as 28 to just two per IC. Its Subclass 1 deterministic latency function is repeatable from power-up cycle to power-up cycle and across link re-synchronisation events. Areas where this function is important are in diversity radio systems and instrumentation, multi-mode digital receiver applications such as TD-SCDMA, WCDMA, LTE (especially the 2R2T >8R8T evolution), radar/defence electronics, medical imaging systems, cable infrastructure and general-purpose software radios.
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