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How to Achieve Power Estimation, Reduction and Verification in Low Power Design

September 27, 2013 // By Kiran Vittal // 0 comments

How to Achieve Power Estimation, Reduction and Verification in Low Power Design Download White Paper 690Ko

Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator.


Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on their long battery lives. In wired applications, power consumption determines heat generation which in turn drives packaging costs. If not managed properly, this may have significant impact on the end appliance cost.

The landscape complicates if we also factor increasing component density of ICs, which leads to progressively increasing power density. The challenge is to pack in more while still consuming less and less power. Semiconductor industry projections indicate a 4-6x increase in leakage power for designs today and all available techniques must be applied to meet the goal that average and standby power remain flat as complexity increases.

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This month Ambiq Micro is giving away five of its 'Apollo EVB' evaluation boards, worth 9 each for EETimes Europe’s readers to assess the capabilities of their cutting-edge Apollo sub-threshold microcontroller.

The new suite of Apollo MCUs is based on the 32-bit ARM Cortex-M4 floating point microcontroller and redefines 'low power' with energy consumption that is typically five to ten times lower than that of MCUs of comparable performance (thanks to Ambiq’s patented Subthreshold Power Optimized Technology platform).


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