IMEC's Apollo makes progress, provides roadmap for spinoff
October 22, 2007 //
Apollo, a three-year strategic research program being pursued by research organization IMEC, is beginning to produce results in its quest to provide the technology for efficient migration to 4G communications and multiprocessing in the sub-45-nm era. It is also set to help drive business at IMECÕs latest spinoff, according to researchers.
LEUVEN, Belgium Apollo, a three-year strategic research program being pursued by research organization IMEC, is beginning to produce results in its quest to provide the technology for efficient migration to 4G communications and multiprocessing in the sub-45-nm era. It is also set to help drive business at IMEC's latest spinoff, according to researchers.
Apollo, a follow-on from IMEC's multimode multimedia (M4) project, started in April and is expected to run through to mid-2010, although a couple of IC tape-outs at 90-nm are still pending as conclusions to the M4 work. Like M4, Apollo is aimed at producing a multi-standard mobile terminal as an industry pathfinder, but while M4 targeted a software defined radio Apollo is expected to move on to a cognitive-radio terminal capable of operating at carrier frequencies up to 60-GHz.
The project is targeting 45-nm IC implementations but is already producing results in terms of architectural considerations for power efficient multiprocessing and design tools, researchers said during press briefings ahead of IMEC's Annual Research Review Meeting last week. In six months the project has produced a multiprocessing support tool and an approach to variability aware design.
Apollo has been organized as eight stand-alone but interlinked technology programs including technology aware design (TAD), processor and compiler architecture, and multiprocessor support, according to Serge Vernalde, technical business director for nomadic embedded systems at IMEC.
The ADRES processor with its VLIW processor and reconfigurable array, which is at the heart of the M4 baseband chip, is likely to be recast under Apollo for multiprocessor deployment. Similarly the Scaldio CMOS analog front end developed for M4 operating at up to 6-GHz will not only get a redesign at that frequency but will be complemented by a 60-GHz CMOS AFE. This is expected to tape-out in 45-nm digital CMOS in the second quarter of 2008, said Liesbet Van der Perre, scientific director for wireless systems.
In addition, the move to Apollo within IMEC adds value to M4S NV (Leuven, Belgium) according to Rudi Lauwereins IMEC vice president responsible for design research. M4S was created to commercialize aspects of the M4 technology. "Apollo provides a roadmap for M4S, said Lauwereins, although Vernalde pointed out that M4S is not the only commercialization route for M4 and Apollo. The Apollo partners also get access although at present IMEC is not revealing names.
Samsung, a key partner in the M4 project and is expected to have renewed its subscription. Meanwhile Qualcomm Inc. has signed on the TAD program within Apollo. The goal of the TAD program is to raise manufacturing reliability and yield issues up to the system design level. Miguel Miranda, a senior scientist at IMEC, explained how relaxing timing constraints can typically improve yield albeit with a minor penalty for average energy consumption.
Even though ultra low energy consumption is a goal of the Apollo project being able to consider yield trade-offs is likely to be valued addition to design optimization particularly as guard-banding for process variation is likely to negate the benefits of process shrinks.
The ADRES processor remains the basic processor for Apollo but extensions are being aimed at upcoming industrial processor architectures, according to Diederik Verkest, science director for design technology at IMEC. "ADRES was already power efficient. With ADRES we can reach 16 to 20 instructions per cycle (IPC). Now we want to see how to embed multiple threads to better fill the array. The target is an IPC count of 50.
Verkest said that IMEC researchers are looking to split ADRES up and separate the controlling VLIW processor from the 4 by 4 array. "We are also investigating commercial solutions, said Verkest. "TI's C64 is a VLIW machine and there are lots of new architectures such as that of Silicon Hive, he added. The reconfigurable array is also likely to go to an 8 by 8 array, providing greater scope for parallelism before putting multiple processors down on silicon.
Therefore extracting parallelism from application software is key to improving performance and power efficiency. To that end IMEC has developed the Multiprocessing Parallelization Assistant (MPA). Based on parallelization directives provided by the designer, the MPA can check a parallelization scheme, insert necessary communication and synchronization primitives and generate code for the multiple processors. Verkest said it is a tool to allow rapid exploration of parallel mappings starting from sequential C code.
In addition IMEC has developed and is supporting ÔCleanC' a coding style with 28 guidelines and restrictions on how to write C code that is multiprocessor friendly, Verkest said. To help software developers adhere to this style IMEC has developed an analysis tool that can analyze software and flag up violations of the CleanC programming style. User-guide code transformations can then be applied to make the code compliant. The tool suite has been integrated into Eclipse 3.3 development environment, specifically within CDT4.0 a version of the C/C++ developer tooling, Verkest said.
See other stories from this issue here.
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