MUNICH, Germany — Peter Flake, formerly chief scientist of Imperas Ltd. (Thame, England), has retired from his post.

Flake, who attended DATE under the banner of his consultancy, Elda Technology, said he had always intended to retire in 2008 but that nonetheless he maintained an interest in computer languages and had come to attend the conference to continue that study. Flake said he was looking at the possibility of an efficient, high-level hardware description language. "It's in the early stages," Flake said.

Flake has been the main research force behind the creation of a software programming and design approach for multiprocessor ICs at Imperas. However, while developing the tools that would allow that Imperas was forced to change its focus.

Simon Davidmann, CEO of Imperas (Thame, England), had previously acknowledged that while customers accept that multiprocessing systems needed improved forms of programming they had more immediate "pain points" in terms of modeling, simulating and debugging the relatively modest multiprocessing SOCs currently in development. Imperas recently put a reference simulator called OVPsim, some high-level processor models into the public domain.

"Yes Peter has retired. We're in a very practical mode of operation right now. We're doing less research and more development. In a small company you can't do research. You have to do engineering," said Davidmann. Davidmann said Imperas would continue to contract-in Flake's services as a consultant and would follow his research progress with interest.

Flake has given many years of service to the EDA industry. At Brunel University in the 1970s he was the architect and project leader that helped developed the first logic simulator, Hilo. It was at this time that Flake was Davidmann's boss as they developed what would be a precursor to the Verilog language developed by Phil Moorby, who had also worked with Flake on Hilo.

After a spell looking after Hilo at GenRad Inc. Flake joined Cadence Design Systems where he developed Verilog simulators and behavioral synthesis tools. Flake left Cadence to work on the Superlog language and helped Davidmann form Co-Design Automation, which was subsequently acquired by Synopsys as Superlog became standardized as SystemVerilog.

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