Improved Memory Throughput Using Serial NOR Flash
March 29, 2012 // Cliff Zitlaw, Spansion // 0 commentsDownload White Paper 1Mo
NOR flash remains the preferred non-volatile technology for discrete memories in embedded systems. Today's NOR based SPI memories have reached 108MHz clock rates with a QuadIO (x4) interface to achieve a 54MB/s sustained read throughput while remaining compatible with the original interface specified nearly 25 years ago. The legacy SPI interface and bus protocol is reaching fundamental timing limits that will make difficult further increases to the SPI bus clock rate. This paper will describe both system level and memory device strategies that deal with these timing limitations allowing higher SPI bus throughputs.
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Linear video channel
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This month, Altium Ltd is offering EETimes Europe's readers the chance to win one TASKING VX-Toolset for ARM Cortex-M Premium Edition, normally licensed for 2.395 Euros, for ultra-rapid prototyping and code development around ARM Cortex-M based microcontrollers.
The VX-toolset for ARM is the first TASKING compiler suite to receive the Software Platform technology, which is seamlessly integrated into the toolset's Eclipse based IDE. The complete offering also includes a C/C++ compiler, simulator and hardware debugger, and a wide collection of frequently used middleware components, such as TCP/IP, USB, CAN, web server, graphical user-interface, and an RTOS. At the cost of a traditional development toolset the developer gets everything needed to build an application much faster than is possible with other compiler suites and additional third party middleware components.
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Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.
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