Improved Memory Throughput Using Serial NOR Flash
March 29, 2012 // Cliff Zitlaw, Spansion // 0 commentsDownload White Paper 1Mo
NOR flash remains the preferred non-volatile technology for discrete memories in embedded systems. Today's NOR based SPI memories have reached 108MHz clock rates with a QuadIO (x4) interface to achieve a 54MB/s sustained read throughput while remaining compatible with the original interface specified nearly 25 years ago. The legacy SPI interface and bus protocol is reaching fundamental timing limits that will make difficult further increases to the SPI bus clock rate. This paper will describe both system level and memory device strategies that deal with these timing limitations allowing higher SPI bus throughputs.
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This month, Trinamic Motion Control is offering you to win one of four TMCM-1043 development kits for its highly integrated, NEMA 17-compatible TMCM-1043 stepDancer stepper motor module.
Offering designers an easy-to-use PC-based GUI that allows one-click modification of motor drive current, micro-stepping and other key parameters, the intuitive kits are custom designed and developed for direct mounting on a NEMA 17 motor. Pre-programmed and pre-configured with all operating parameters to support standard 1.5A (peak) motors, the TMCM-1043 board uses Trinamic´s single-axis TMC2660 stepper motor driver IC, which integrates a motor pre-driver and power MOSFETs.
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