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Intel exec claims fabless model “collapsing”

April 25, 2012 // Rick Merritt

Intel exec claims fabless model “collapsing”

It’s the beginning of the end for the fabless model according to Mark Bohr, the man I think of as Mr. Process Technology at Intel.

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Bohr claims TSMCs recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed mitigate leakage current, Bohr said.

Qualcomm wont be able to use that [20 nm] process, Bohr told me in an impromptu discussion at yesterdays press event where Intel announced its Ivy Bridge CPUs made in its tri-gate 22 nm process. The foundry model is collapsing, he told me.

Of course Intel would like the world to believe that only it can create the complex semiconductor technology the world needs. Not TSMC that serves competitors like Qualcomm or GlobalFoundries that makes chips for Intels archrival AMD.

Intel used the Ivy Bridge event to spin the tale of how part of the secret to its success is its close partnership between process and chip designers.

Kirk Skaugen, the new general manager of Intels client PC group, moderated a Q&A with Bohr and Brad Heaney, the Ivy Bridge program manager. In addition to working together on Intels first CPUs using 3-D transistors, the two collaborated on Intels first processors using high-K metal gate technology.

Being an integrated device manufacturer really helps us solve the problems dealing with devices this small and complex, Bohr said in the Q&A.

I dont doubt that for a minute. Since the dawn of submicron design, EE Times has been writing about the need for ever closer collaboration between chip and process designers. An Nvidia physical design exec underlined the same point in a recent talk at Mentor Graphics annual user group meeting.

But Bohr stretches the point too far when he says the foundries and fabless companies wont be able to follow where Intel is going. I have heard top TSMC and GlobalFoundries R&D managers make a good case that 3-D transistors wont be needed until the 14 nm generation. For its part, TSMC said at 20 nm there is not enough wiggle room to create significant variations for high performance versus low power processes.
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