Intel FinFETs may need SOI to shrink

June 08, 2012 // Peter Clarke

Intel's 22-nm FinFETs show physical variability according to cross-sectional photographs from engineering consultancy Chipworks Inc., (Ottawa, Ontario) and EDA company Gold Standard Simulations Ltd., (GSS) has attempted to model electrical characteristics of various examples.

One conclusion drawn by Professor Asen Asenov, CEO of GSS (Glasgow, Scotland), is that Intel may need to turn to silicon-on-insulator wafers to scale its FinFETs below 22-nm. This may also have implications for foundries which are yet to introduce FinFET technology into their chip manufacturing processes.

GSS has already done some TCAD simulation of FinFETs and posted findings in a blog that discussed the fact that at 22-nm Intel's FinFETs are trapezoidal rather than rectangular in cross-section (see Intel's FinFETs are less fin and more triangle).

The latest GSS blog seeks to compare the on-current of differently-shaped FinFETs. It points out that in logic applications multiple fins are connected in parallel, resulting in an averaging of their characteristics, but in SRAM circuits the variability of a single fin is a key characteristic and performance limiter.



TEM images of three Intel FinFETs with the GARAND simulation domain overlaid. Source: GSS


The characteristic dimensions of three FinFETs were fed into the GSS Garand simulator and it revealed that at 22-nm, nature appears to have worked to Intel's advantage. "Despite significant differences in the shape of the three fins, the difference in the on-current is within a 4 percent range," the blog states.

"Compared with process variation across the chip or across the wafer 4 percent is small. But it is additional variation," Professor Asenov told EE Times. He added that the simulation revealed that the FinFET process technology is complex and difficult to implement, partly because of the lack of a planarization process that can level-up shallow trench isolation oxides between transistors. One result of this is that bulk FinFET heights can vary, he said.

Professor Asenov admitted that a number of assumptions have to be made to allow the simulations to run. It is assumed that the fin itself is virtually undoped but there is a punch-through stopper dopant region beneath the fin. "We don't know about dopant profiles and strain, but we have tried to make favorable assumptions," said Professor Asenov.



Dependence of on-current, ION, on gate length. Source: GSS.


GSS has included results for simulations of rectangular cross-section FinFETs with 10-nm and 8-nm widths hinting at where the company thinks Intel must go next. "If you can make them [FinFETs] rectangular you will gain significantly in terms of performance, about a 20 percent gain."

Professor Asenov said that moving from bulk FinFETs to FinFETs constructed on SOI wafers could solve a number of problems. "The buried oxide layer means you don't have the problem of filling trenches. The height of the fin is determined by the depth of the silicon above the oxide."

Professor Asenov added: "I think Intel just survived at 22-nm. I think bulk FinFETs will be difficult to scale to 16-nm or 14-nm. I think that SOI will help the task of scaling FinFETs to 16-nm and 11-nm. Of course, the wafers are more expensive, but you save money with less processing."

Researchers from GSS and the University of Glasgow published a paper at the International Electron Devices Meeting of 2011 that dealt with FinFETs implemented in SOI wafers and how they could meet the low statistical variability requirements of 11-nm CMOS.


GSS blog
www.goldstandardsimulations.com
www.chipworks.com

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