Intel gives deeper look into Ivy Bridge

February 21, 2012 // Rick Merritt

Intel gave its first details public look into Ivy Bridge, the first processors to use its 22 nm tri-gate technology. Intel plans at least four major variants of the chip which packs 1.4 billion transistors into 160mm-squared in its largest version.

Ivy Bridge packs 20 channels of PCI Express Gen 3 interconnect and a Displayport controller, Intel’s first chip to integrate PCIe. The move marks one small step into the long term quest of what an Intel executive called terascale-class clients.

The first Ivy Bridge chip targets a range of desktop, notebook, embedded and single-socket server systems with up to 8 Mbytes cache. Like previous Intel parts it integrates a memory controller and graphics, now upgraded to support DDR3L DRAMs and Microsoft DirectX 11.0 graphics APIs.

“We spent a lot of time on the modularity of this die to create different flavors of it very quickly,” said Scott Siers, an Intel engineer who presented a paper on the chip at the International Solid-State Circuits Conference.

Specifically the largest die includes four x86 cores and a large graphics block. It can be chopped along its x- and/or y-axis using automated generation tools to create versions with two cores or a smaller graphics block.

Siers said Ivy Bridge is Intel’s first client chip to support low power 1.35-V DDR3L and DDR power gating in standby mode. It handles up to 1,600 MTransfers/s as well as 1.5V DDR3. A new write assist cache circuit provides an average 100 millivolt power reduction.

The Displayport block supports three simultaneous displays including one 1.6 GHz and two 2.7 GHz links with four lanes each.

The PCIe receiver uses a continuous time linear equalizer with 32 gain control levels and a transmitter with a three-tap digital FIR filter. The PCIe block also supports on die testing for jitter as well as timing and voltage margin measurements.

The chip’s x86 and graphics cores can scale in data rates at 100 and 50 MHz increments respectively. Overall, the chip supports five power planes and 180 clock islands that can be separately gated.

In a separate ISSCC keynote, Dadi Perlmutter, chief product officer for Intel, scoped out a long term vision of terahertz-class clients. Terahertz systems consume as much as three kilowatts today but could be reduced to 20 W by the end of the decade using a broad variety of techniques, he said.

The techniques include optimizing chips to work at near threshold voltage levels, a subject of several Intel papers at ISSCC. Lower power internal and external interconnects are also needed, he said.

3-D IC packaging will be needed to lower power memory, Permutter said. Toward that end Intel is working with Micron and others on its Hypercube stacked memory design, he said. The design could boost memory bandwidth ten-fold while cutting power to eight pico-joules per bit, down from 50-75 pj/bit in today’s DDR3, he added.

In addition, “voltage regulation has to go into the IC itself because inductance is too big off chip or even on package,” Perlmutter said. “When you have a lot of voltage regulators to turn on and off it becomes very complex to do on a package, so we are working on getting power regulators into the ICs,” he said.

Perlmutter said he sees another 30 years of engineering needed in computing. “For people who thought they could retire from this industry, I say there’s a lot more to do,” he said.

Technical papers     

• AR RF/Microwave Instrumentation Field Analyzers
• 16-Bit, 100 kSPS Low Power Successive Approximation ADC System
• Replacing the Candle in the Candelabra
• Adaptive Cell Converter Topology Enables Constant Efficiency in PFC Applications

December 15, 2011 | Texas instruments | 222901974

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