Lattice and Helion release HD HDR IP cores video security and surveillance cameras
July 06, 2010 // Paul Buckley
Lattice Semiconductor and Helion GmbH have released Intellectual Property (IP) cores for the video security and surveillance camera market. Targeting the LatticeXP2, LatticeECP2M and LatticeECP3 FPGA families, Helion has demonstrated its IONOS video pipeline IP and Vesta evaluation platform.
Helion offers a comprehensive selection of video pipelines, ranging from basic to advanced monochrome and color pipelines, all the way through high resolution advanced High Dynamic Range Imaging (HDRI) color pipelines. Depending on the pipeline selected, it will consist of a number of individual video processing IP cores, such as defective pixel correction, logic-efficient 3 x 3 De-Bayering, high quality 5 x 5 De-Bayering, color-correction matrix, gamma correction, auto-exposure, auto-white balance and more. These cores also support Lattice FPGA devices, and all are compatible and simply connected using the Wishbone bus.
LatticeXP2, ECP2M and ECP3 FPGAs support several image preprocessing functions for a number of image sensors from VGA to 12 MP, said Dr. Arndt Bussmann, Chief Technical Officer at Helion GmbH. The Wishbone bus makes it easy to combine and connect our various IONOS IP cores according to customer needs. That makes it easier to link different IP cores with each other and to use the appropriate FPGA, ranging from a small XP2 FPGA for a simple preprocessing unit, like monochrome VGA with our Fast Auto Exposure, up to an ECP2M or ECP3 FPGA with full HD or 12MP color pipe, including HDR. This combination of the Lattice FPGA, the Wishbone architecture and our IONOS IP cores is a very effective way to get an economical and customized image processing unit. All news
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