Lattice releases ultra-low power IspLEVER Classic design tool suite
October 17, 2011 // Paul Buckley
Lattice Semiconductor Corporation has introduced its ispLEVER Classic version 1.5 design tool suite which continues to support the ultra-low power ispMACH 4000ZE CPLD family as well as all of Lattice's mature programmable devices, including GAL and ispGAL Simple PLDs (SPLDs); ispLSI, MACH, ispMACH and ispXPLD Complex PLDs (CPLDs); ORCA, FPSC and ispXPGA Field Programmable Gate Arrays (FPGAs); and ispGDX/ispGDX2 crosspoint devices.
Lattice's ispLEVER Classic 1.5 design software includes everything necessary to take a project from concept through to a programmed device and provides a powerful set of software tools for all design tasks, including project management, HDL design entry, module/IP integration, place and route, timing analysis, in-system logic analysis and much more.
Tool reporting has been improved with version 1.5, to make it easier to interpret. The Windows 7 64-bit OS is also now fully supported. Lattice also works closely with industry leaders Synopsys and Aldec to provide superior HDL synthesis and simulation solutions, fully integrated into the ispLEVER Classic design flow.
The new Windows-based version is now available for download and licensing at no charge from the Lattice website: www.latticesemi.com/ispleverclassic
Rohm buys Renesas wafer fab
May 25, 2015
Rohm Co. Ltd. (Kyoto, Japan) has moved to acquire a 200mm wafer fab from Renesas Electronics Corp. for 450 million yen (about ...
SK Hynix, Sharp move up chip vendor ranking
IDT partners EPC to integrate GaN and silicon technologies
Reduce EMI with 42-V, 5-A synchronous step-down silent switcher
Egg-shaped micro home runs on wind, solar power
Extensible CPU cores exploit IoT's vast potential
May 22, 2015
Cisco Systems has predicted that by 2020, there will be 50 billion “things” connected to the Internet up from 15 billion ...
Audi connects to Baidu, Huawei at CES Asia
LED roadway solutions focus on rural, remote communities
New class of magnets attract energy harvesting attention
- Integrating GPS into consumer products
- Controlling LED Lighting Using Triacs and Quadracs
- Automotive Designs Demand Low EMI Synchronous Buck Converters
- Smart Capacitive Design Tips
InterviewCEO interview: What's next after Tower's turn-around?
May 2015 marks the tenth anniversary of Russell Ellwanger taking over as CEO of speciality foundry Tower Semiconductor Ltd. (Migdael Haemek, Israel), which now trades as TowerJazz. And so EE Times Europe ...
Filter WizardCheck out the Filter Wizard Series of articles by Filter Guru Kendall Castor-Perry which provide invaluable practical Analog Design guidelines.
Linear video channel
READER OFFERRead more
In this month's reader offer, Analog Devices is giving away five Blackfin Low-Power Imaging Platform (BLIP) Development Systems (ADZS-BF707-BLIP2), worth 199 dollars each, for EETimes Europe's readers to win.
Targeting demanding ultra-low-power, real-time applications for image sensing and advanced audio, the development platform leverages the company’s ADSP-BF707BBCZ-4 Blackfin processor as...MORE INFO AND LAST MONTH' WINNERS...
December 15, 2011 | Texas instruments | 222901974
Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.