Lattice releases ultra-low power IspLEVER Classic design tool suite
October 17, 2011 // Paul Buckley
Lattice Semiconductor Corporation has introduced its ispLEVER Classic version 1.5 design tool suite which continues to support the ultra-low power ispMACH 4000ZE CPLD family as well as all of Lattice's mature programmable devices, including GAL and ispGAL Simple PLDs (SPLDs); ispLSI, MACH, ispMACH and ispXPLD Complex PLDs (CPLDs); ORCA, FPSC and ispXPGA Field Programmable Gate Arrays (FPGAs); and ispGDX/ispGDX2 crosspoint devices.
Lattice's ispLEVER Classic 1.5 design software includes everything necessary to take a project from concept through to a programmed device and provides a powerful set of software tools for all design tasks, including project management, HDL design entry, module/IP integration, place and route, timing analysis, in-system logic analysis and much more.
Tool reporting has been improved with version 1.5, to make it easier to interpret. The Windows 7 64-bit OS is also now fully supported. Lattice also works closely with industry leaders Synopsys and Aldec to provide superior HDL synthesis and simulation solutions, fully integrated into the ispLEVER Classic design flow.
The new Windows-based version is now available for download and licensing at no charge from the Lattice website: www.latticesemi.com/ispleverclassic
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