Low power CMOS platform helps reduce IC power consumption by more than 50 percent
June 07, 2011 // Paul Buckley
SuVolta, Inc., has introduced its PowerShrink low-power platform which reduces the power consumption of CMOS ICs by 2x or more while maintaining performance and improving yields. Fujitsu Semiconductor Limited has also licensed SuVoltaís innovative PowerShrink low-power technology.
SuVolta has demonstrated large SRAM blocks operating below 0.5 volts, thereby confirming that the DDC transistor enables circuit functionality at far greater than 30 percent VDD scaling. The sub-0.5 volt operating voltage is among the lowest reported for 65 nm CMOS technology, and is significantly lower than typical SRAM minimum operating voltages (VDD-min) of 0.8 volts and higher in conventional CMOS technologies.
Controlling power consumption is a key enabler for adding features to IC products and for scaling semiconductor process technologies. SuVoltas Deeply Depleted Channel transistor uses a channel structure with significant benefits for low power operation compared to conventional transistor technology. By reducing threshold voltage (VT) variation by 50 percent, the DDC transistor enables scaling of supply voltage (VDD) by 30 percent (or more) while maintaining the same system clock speed and reducing overall leakage. By increasing channel mobility, the DDC transistor increases drive current (Ieff) by 10 percent or more. In addition, the DDC transistor enables even more effective threshold voltage management through body biasing by dramatically increasing body coefficient.All news
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