Low power CMOS platform helps reduce IC power consumption by more than 50 percent
June 07, 2011 // Paul Buckley
SuVolta, Inc., has introduced its PowerShrink low-power platform which reduces the power consumption of CMOS ICs by 2x or more while maintaining performance and improving yields. Fujitsu Semiconductor Limited has also licensed SuVolta’s innovative PowerShrink low-power technology.
The PowerShrink low-power platform consists of SuVolta’s Deeply Depleted Channel (DDC) CMOS transistor technology as well as DDC-optimized circuits and design techniques that take full advantage of the DDC transistor properties. The platform enables supply voltage reductions of 30 percent or more – cutting dynamic power consumption in half (or more) – while maintaining performance, and can reduce leakage power consumption by 80 percent (or more). These benefits apply across a wide range of IC products, including processors, SRAMs, and SOCs that are critical to today’s mobile products.
SuVolta has demonstrated large SRAM blocks operating below 0.5 volts, thereby confirming that the DDC transistor enables circuit functionality at far greater than 30 percent VDD scaling. The sub-0.5 volt operating voltage is among the lowest reported for 65 nm CMOS technology, and is significantly lower than typical SRAM minimum operating voltages (VDD-min) of 0.8 volts and higher in conventional CMOS technologies.
Controlling power consumption is a key enabler for adding features to IC products and for scaling semiconductor process technologies. SuVolta’s Deeply Depleted Channel transistor uses a channel structure with significant benefits for low power operation compared to conventional transistor technology. By reducing threshold voltage (VT) variation by 50 percent, the DDC transistor enables scaling of supply voltage (VDD) by 30 percent (or more) while maintaining the same system clock speed and reducing overall leakage. By increasing channel mobility, the DDC transistor increases drive current (Ieff) by 10 percent or more. In addition, the DDC transistor enables even more effective threshold voltage management through body biasing by dramatically increasing body coefficient.
“Up to this point in time, semiconductor process technology innovation has primarily focused on increasing performance. But the biggest problem in semiconductors today is not performance but power. SuVolta is solving the power impasse by significantly reducing transistor threshold voltage variation and therefore enabling supply voltage scaling,” said Scott Thompson, CTO at SuVolta. “SuVolta’s DDC submicron technology addresses threshold voltage control by limiting random and other sources of dopant fluctuation while simultaneously improving carrier mobility and reducing device capacitance so as to maintain circuit speed at much lower power.”
The SuVolta PowerShrink low-power platform is compatible with current manufacturing and design infrastructure. SuVolta’s DDC transistor leverages existing CMOS design rules and process flows, and can be manufactured in existing fabs because it does not require new equipment or new materials. SuVolta’s PowerShrink platform also uses conventional design tools and design flows.
SuVolta’s circuits and design techniques take advantage of the properties of the DDC transistor to reduce power consumption further, by managing VT more effectively than possible with a conventional transistor. Adaptive body biasing can be used to correct systematic manufacturing variations, thus further decreasing VT variation and improving sort yield. Dynamic body biasing can be used to reduce temperature and aging effects, and to make power modes more effective at enabling low power operation.
Visit SuVolta at www.suvolta.com.
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