Print  |  Send  |   

Low Power Design – where next for Power-Gating?

January 18, 2012 // David Flynn, ARM // 0 comments

Low Power Design – where next for Power-Gating? Download White Paper 835Ko

On-chip power gating is well understood and supported by multi-voltage EDA tools and Unified and Common Power Formats (UPF and CPF), but has limitations. This paper describes new techniques, developed and evaluated in silicon in R&D at ARM, that enhance power gating and address state retention with minimal area and performance impact. Appropriate for Cortex-A class to Cortex-M class SOC designs.


All White Papers


Submit a white paper

Follow us

Fast, Accurate & Relevant for Design Engineers only!

Technical papers     

Linear video channel

READER OFFER

Read more

In this month's reader offer, Analog Devices is giving away five Blackfin Low-Power Imaging Platform (BLIP) Development Systems (ADZS-BF707-BLIP2), worth 199 dollars each, for EETimes Europe's readers to win.

Targeting demanding ultra-low-power, real-time applications for image sensing and advanced audio, the development platform leverages the company’s ADSP-BF707BBCZ-4 Blackfin processor as well as ADI’s optimized software libraries for video occupancy sensing.

MORE INFO AND LAST MONTH' WINNERS...

Design centers     

Automotive
Infotainment Making HDTV in the car reliable and secure

December 15, 2011 | Texas instruments | 222901974

Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.

 

You must be logged in to view this page

Login here :