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Low Power Design – where next for Power-Gating?

January 18, 2012 // David Flynn, ARM // 0 comments

Low Power Design – where next for Power-Gating? Download White Paper 835Ko

On-chip power gating is well understood and supported by multi-voltage EDA tools and Unified and Common Power Formats (UPF and CPF), but has limitations. This paper describes new techniques, developed and evaluated in silicon in R&D at ARM, that enhance power gating and address state retention with minimal area and performance impact. Appropriate for Cortex-A class to Cortex-M class SOC designs.


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The SoCKIT evaluation kit is Arrow's latest development tool, featuring an Altera Cyclone V SoC with a dual-core ARM Cortex-A9 MPCore processor integrated within its 28nm FPGA fabric.

Altera SoCs allow embedded system developers to differentiate their end product with customized hardware and software, and extend the product lifecycle through hardware and software updates in the field. This month, Arrow Electronics is giving away five SoCKIT evaluation kits featuring Altera’s ARM-Based SoCs, worth €249 each, together with the free entrance to one of Arrow’s SoC workshops organized throughout Europe.


And the winners are...

In our previous reader offer, Freescale Semiconductor was giving away five IMX6Q, Sabre-lite kits, worth £128.06 each.

Lucky winners include Mr. X. Salada Sole from the UK, Mrs A. Peric from Germany, Mr Z. Janosy from Hungary, Mr D. Gacina from Croatia and Mr B. Boris from France. All should be receiving their packages soon. Let's wish them some interesting findings with their projects.


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