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Low Power Design – where next for Power-Gating?

January 18, 2012 // David Flynn, ARM // 0 comments

Low Power Design – where next for Power-Gating? Download White Paper 835Ko

On-chip power gating is well understood and supported by multi-voltage EDA tools and Unified and Common Power Formats (UPF and CPF), but has limitations. This paper describes new techniques, developed and evaluated in silicon in R&D at ARM, that enhance power gating and address state retention with minimal area and performance impact. Appropriate for Cortex-A class to Cortex-M class SOC designs.


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This month Ambiq Micro is giving away five of its 'Apollo EVB' evaluation boards, worth 9 each for EETimes Europe’s readers to assess the capabilities of their cutting-edge Apollo sub-threshold microcontroller.

The new suite of Apollo MCUs is based on the 32-bit ARM Cortex-M4 floating point microcontroller and redefines 'low power' with energy consumption that is typically five to ten times lower than that of MCUs of comparable performance (thanks to Ambiq’s patented Subthreshold Power Optimized Technology platform).


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