Low power LatticeECP4 FPGAs start shipping
June 08, 2012 // Paul Buckley
Lattice Semiconductor Corporation has begun shipping the highest density member of the company’s next generation LatticeECP4 FPGA family to select customers.
The highest density device in the family, the LatticeECP4-190, features 183K LUTs, 480 double data rate DSP multipliers (18x18), 5.8 Mbits of memory and twelve 6 Gbps SERDES channels, making it ideally suited for a broad range of cost- and power-sensitive wireless, wireline, video and computing applications. Lattice has released three flip-chip packages for the LatticeECP4-190 (676, 900 and 1152 pins) that are well suited for a wide range of applications.
The LatticeECP4-190 FPGA offers high-speed CPRI and SRIO 2.1 interfaces and double data rate digital signal processing (DSP) blocks for building heterogeneous wireless networks. The LatticeECP4 FPGAs facilitate rapid construction of the latest 3G/4G metro basestations, small cell stations, pico stations, microwave and millimeter-wave backhaul links.
The LatticeECP4-190 FPGA also provides wireline access developers with 36 embedded clock and data recovery (CDR) circuits to build high port density switches and routers using innovative low cost, low power FPGAs. The DSP blocks and a growing portfolio of third-party intellectual property cores and reference designs are also enabling video and surveillance camera customers to implement complex algorithms using affordable, mid-range FPGAs.
"With the silicon release of our LatticeECP4-190 devices, our customers can implement even more complex designs for wireless base stations and backhaul, wireline access, video and display applications and still benefit from the devices low power and economy," said Sean Riley, Lattice Corporate Vice President and General Manager, Infrastructure Business Unit. The next generation LatticeECP4 FPGA family brings premium features to infrastructure customers while maintaining industry-leading low power and low cost.All news
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