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MIPI M-PHY takes center stage

June 24, 2010 // Ashraf Takla and George Brocklehurst

MIPI M-PHY takes center stage

The curtain is up and the M-PHY specification is taking center stage, positioned to handle the many different roles required for a faster, more reliable, physical interface layer (PHY Layer) on mobile devices.


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The script for the M-PHY specification was written inside the MIPI (Mobile Industry Processor Interface) Alliance by a working group made up of member companies, and set up to expand the capabilities of mobile devices by defining interface standards that will revolutionize the capabilities of the coming generations of mobile products. Faced with an explosion of mobile multimedia devices, with an ever increasing demand for faster throughput, the mobile industry, through the MIPI Alliance, has defined the ultimate PHY, one capable enough to handle the demands of mobile devices and seemingly capable of moving into several other key application areas as the PHY of choice.

MIPI and the M-PHY

The M-PHY specification is an essential part of the MIPI Alliances vision for new and more capable high-speed interfaces on mobile devices. Members identified early the need for a serial interface to support the ever increasing data bandwidth requirements of mobile devices. Now, pressed even further by the explosion of digital content in video, social media exchanges, and cloud computing, mobile devices require a faster physical layer interface, like the M-PHY, to remain a step ahead of the data transfer requirements necessary to give consumers the on-device response they need. Fuelled by the success of the other MIPI Standards now being deployed, the M-PHY specification is gaining momentum as it moves toward final approval as the newest MIPI specification. The MIPI D-PHY, a source synchronous interface that is currently handling the interfaces between the application processor chip and the camera or display in a mobile device, has been especially successful.

Even though the D-PHY is a capable interface, its synchronous nature has speed limitations (1 Gigabit per second) that prevent it from handling the demands for higher data transfer rates. The industry requires a more powerful PHY, one that offers asynchronous data transmission and addresses the speed and signal integrity issues of high-speed chip-to-chip connections within an increasingly EMI (Electro-Magnetic Interference) sensitive environment compounded by tighter form factors, while continuing to minimize power dissipation.

The M-PHY plays many roles

Just like a versatile star, the M-PHY interface is talented enough to play many roles. When first envisioned, it handled the set of specifications already defined or in the process of being defined inside MIPI. Those specifications included the Camera Serial Interface (CSI), the Display Serial Interface (DSI), and a Universal Protocol (UniPro). The CSI and DSI specifications are easily understood: they define the protocol interfaces between the application processor and a camera or a display. UniPro (Universal Protocol) is a comprehensive specification meant to act as a universal chip-to-chip protocol, providing a common tunnel for other protocols.

The M-PHY interface is designed as the primary physical interface (PHY layer) for the UniPro specification. The M-PHY specification has two signaling schemes, supporting both self clocking and embedded clocking. Additionally it runs at both lower and higher speeds. The high-speed communication option makes the M-PHY interface the perfect vehicle for UniPro offering speed, power and economy.

The first evidence of the M-PHY interface versatility emerged when the DigRF Alliance was assimilated into MIPI. The DigRF Alliance had defined a specification between the Baseband (BBIC) and the RF chip (RFIC) for mobile platforms. This new specification describes the logical, electrical and timing characteristics of the digital BBIC to RFIC interface. Accepting the role as the new physical interface is the M-PHY.

The M-PHY interface was further recognized by JEDEC as an ideal physical layer for its highly anticipated Universal Flash Storage (UFS) specification, defining a high-level interface that standardizes connectivity in an extensive range of diverse, non-volatile memory solutions currently being developed within the JC-64 Committee on Flash Memory Modules. The M-PHY is the perfect player for the PHY layer specification.

Building on this successful start, another subcommittee within JEDEC, the Low Power Memory J42.6 subcommittee, is also considering the M-PHY for yet another role as the Physical Layer for future Mobile.

The M-PHY specification, when finalized, will provide a physical layer that shall always be used in combination with a higher layer MIPI specification that references it. Any other use of the M-PHY specification is strictly prohibited, unless approved in advance by the MIPI Board of Directors.

The character of the M-PHY

The M-PHY is defined as a serial link. The overall objectives fall into this general requirements list:

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