Modelling Non-Linearity in Timing Analysis
The fabrication units take time to mature a particular technology node due to these rapid changes and this impacts the maturity of models used to characterize the circuit delays and other timing data.
Due to this, different static timing analysis (STA) and circuit optimization techniques are emerging, providing important avenues to account for the increasing process variations in SoC design. Not only this, new techniques of characterized circuit data modeling are also emerging.
The STA team has to consider some design margins and uncertainties in timing closure at synthesis, place & route and sign-off stage to take account of these modeling uncertainties.
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