Multi-core processor for LTE eNodeB / base stations

February 15, 2011 // Julien Happich

The XLP316L multi-core, multi-threaded processor designed by NetLogic Microsystems is optimized to deliver the highest performance for next-generation LTE base stations. The multi-core processor integrates sixteen NXCPUs, and features a breakthrough quad-issue, quad-threaded and superscalar out-of-order processor architecture capable of operating at up to 2.0GHz.

The XLP316L processor will be manufactured in the advanced 40nm process, and is targeted to offer unparalleled performance of 20Gbps and 30 million packets-per-second (Mpps) for converged data plane and control plane processing in LTE and LTE-Advanced base stations.

In addition, the sixteen NXCPUs are fully cache and memory coherent for software applications to seamlessly run in Symmetric Multi Processing (SMP) or Asymmetric Multi Processing (AMP) modes. The unique combination of superior processor cores and scalability to sixteen NXCPUs makes the XLP316L the industry's highest performance multi-core communications processor, claims the manufacturer.

The XLP316L processor features NetLogic Microsystems' high-speed, low-latency Enhanced Fast Messaging Network to enable efficient, high-bandwidth communication among the sixteen NXCPUs and to support billions of in-flight messages and packet descriptors between all on-chip elements.

The XLP316L multi-core processor offers a tri-level cache architecture with over 6 Mbytes of fully coherent on-chip cache which delivers 40 Tbps of extremely high-speed on-chip memory bandwidth.  The XLP316L processor also incorporates one channel of 72-bit DDR3 interconnect that yields over 100 Gbps of off-chip memory bandwidth.

To complement the sixteen NXCPUs, the XLP316L processor offers fully-autonomous processing engines that provide independent and complete offload of certain network functions from the NXCPUs, including 10Gbps of encryption/decryption/authentication including support for Kasumi and SNOW3G protocols that are required for mobile infrastructure, ingress/egress packet parsing and management, packet ordering, TCP segmentation offload and IEEE 1588 hardware time stamping.

The chip integrates advanced wireless security technologies to support SNOW3G and KASUMI protocols, multiple lanes of Serial Rapid I/O (SRIO) interfaces, and IEEE 1588v2 hardware time stamping for Ethernet backhaul timing synchronization, thereby further enhancing the performance, flexibility and functionality of the multi-core processor for LTE applications.

NetLogic Microsystems at www.netlogicmicro.com

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