New 16-Bit ADCs focus on high performance, wide bandwidths and ease of use
October 04, 2010 // Paul Buckley
Talking to Paul Buckley, EE Times Europe Power Managementís editor, Jon Hall Analog Devicesí Strategic Marketing & Applications Manager High Speed Converters, explains the key features and benefits of the AD9467 16-Bit ADC.
Aiming to take signal processing performance for communications, test and measurement and defense electronics applications to a new level Analog Devices, Inc., (ADI) recently released a 16-bit analog-to-digital converter (ADC) which the company claims now makes the device the industry’s fastest ADC.
The new AD9467 ADC features a maximum sampling rate of 250 MSPS which ADI claims is up to 25% faster than its nearest rival. In addition, the company is also claiming power savings of up to 40% for the new 16-bit ADC.
Claiming a high spurious-free dynamic range (SFDR) of up to 100 dBFs (90 dBFs up to 300 MHz) the AD9467 is also offering a signal-to-noise ratio (SNR) performance of 76.4 dBFS.
The new ADC is initially targeting applications such as radar systems, spectrum analyzers and multi-carrier, multi-mode receiver designs for wireless infrastructure equipment that are defined by high resolution and throughput. The device’s SFDR performance and 60-femtosecond rms jitter allow engineers to increase system performance even as they reduce the size of their equipment.
EE Times Europe: What are the key features and benefits of the new high performance 16-bit ADC?
Hall: The device is the first 16-bit 250 MSPS ADC out there. We are actually offering two speed grades. One operates at 200 MSPS and one is at 250 MSPS. They have also been optimized from a power and performance stand point.
Our linearity, which translates to high frequency SFDR, is able to support a higher IF sampling range than our nearest competitor (an 11 dB improvement at 170 MHz input) while still maintaining a high performance.
What the AD9467 also brings to the table is 76.4 dBFs SNR, high spurious free dynamic range (SFDR) at 100dBFs and very good aperture jitter (60 fsec RMS jitter) that helps with IF sampling or supporting higher input frequencies.
There are also power benefits as well as sampling rate advantages which translate into bandwidth support. We have also incorporated ease of use features. The AD9467 has a buffer on it. Given the dimensions or the performance specs a buffer is advantageous from a systems implementation point of view. From an analog input perspective the buffer reduces the switching transients that occur in any high-speed A-to-D and how they impact any drive circuitry. The buffer helps there but what we did is add a programmability feature to the buffer, which is programmable through our serial port interface, where you can optimize the buffer setting based on the application or the input frequency that your system is set up at. So we will have some knobs there that the designer can take and optimize based on the higher frequency planning that they have.
All of ADI converters have a serial port memory map and that has not changed. We have a fixed customer memory map that we dovetail into that for this device for ease of use from a software perspective.
EE TIMES Europe: How did you set about achieving the improvements in sampling rate?
Hall: The improvement in the sampling rate is the nature of the ADC pipeline. This is not an interleaved solution. This is a standard pipeline device. We designed the front-end to support the IF sampling at 250 MSPS. So it was right out of the chute. The definition was to target that sample rate. The stages in the pipeline have been designed to meet those timing requirements over temperature and supply.
EE TIMES Europe: What applications will this ADC address?
Hall: Although the ADC is targeted as an open market part we have already engaged with a set of customers ahead of the launch to try teach them how to achieve the performance at a systems level while enabling us to learn the kind of problems they are going through so as to allow us to better serve a larger audience when we introduce the part.
What are we bringing to the table from an application perspective? We engaged with customers ahead of time across three market segments:
- The wireless infrastructure sector
- The test equipment (spectrum analysis) sector
- The military and defense sector
I guess essentially given the SNR and spurious free dynamic range the receive function of any of these systems has just been incrementally improved and there are system benefits there that are different dependent on the end market.
There is improved radio sensitivity in the wireless infrastructure. The SFDR allows you to build a common radio platform that might serve a multi-carrier GSM frequency band and the stringent requirements there for Class 1 in terms of blocking spec.
In the test equipment segment it is pretty simple. They always want more bits – faster. They just want to have spectrum analyzers capable of supporting a wider bandwidth and have better dynamic range and better SNR for testing purposes.
The defense and aerospace engineers are essentially making spectrum analyzers in the form of a radar and do this they will marry up multiple high-speed ADCs and will either sum them up so that it is a summing function for land-based or maritime-based, sea worthy radar systems.
They are always trying to increment, in terms of sensitivity, acquisition of targets. As well as discerning different targets based on some digital processing technique they have and they keep secret.
So there are lots of different benefits but it all depends on the performance of the ADC and how it performs in these sub-segments.
EE TIMES Europe: Can you identify some early adopters of the ADC?
Hall: We did engage with one company by the name of Mercury Computer Systems. They build data acquisition cards and essentially the company's creates data acquisition card solutions. The company is focused on military/aerospace applications. What results is a proof of concept through these data acquisition cards and then the company will typically do a custom job for a particular project.
Brian Kimball, Principal HW Engineer at Mercury Computer Systems told us: “We needed a 16-bit, 250-MSPS data converter with 90 db of SFDR for one of our key customer's highly advanced, data acquisition systems. The AD9467 data converter was designed into this customer's system because it met our SFDR, ENOB, and power requirements. Analog Devices worked with us as trusted advisors to provide early-access silicon and design support to enable the timely development of our prototype product.”
What caught MCS' customer's attention was their system's performance based on our ADC. We've been working with Mercury for a couple of quarters now in terms of early engagement and early samples for them. It has been very successful for them.
National Instruments is basically taking different tack. The company is also building card based systems but it is really focused on test equipment. National Instruments has a platform called FlexRIO and the fact that the power consumption is lower than what is out there today allows them to put this ADC on the board and still meet a power budget per card. The device basically enables the FlexRIO product family to support higher spectrum analyzer type needs.
Phil Hester, Senior Vice President of R&D, National Instruments is pretty happy with that. We've been engaged with National Instruments for two quarters now. Hester said: “The AD9467 converter is attractive to NI because of its industry-leading combination of sample rate and resolution. We are currently developing a module based on the AD9467for our NI FlexRIO product family, which couples this new performance point with FPGAs that can be programmed with LabVIEW. The AD9467 helps us maintain leadership in providing innovative solutions for test and measurement, software-defined radio, medical imaging, and scientific research applications.”
EE TIMES Europe: How did you achieve the power saving?
Hall: There is an element of design technique and how you biase the pipeline as you work your way down through the pipe. But there is also an element of the process node that you choose for high-speed ADCs. If you think about it from a power perspective we added a buffer which adds power so we had to make that trade-off and, say OK, if there is a buffer on the chip there is going to be some impact on the power consumption. With the trade-off there is an advantage for achieving the system performance from a customer perspective. We can have lower power without a buffer but it is harder to use. So we made a trade-off. Primarily, the factors for the power savings were the process node that we are on which is 0.18 and the design techniques that we have used in terms of biasing the pipe appropriately as you work your way down through the pipe.
EE TIMES Europe: Are you offering an evaluation system?
Hall: We recognize that we need to supply the kind of information that makes a design engineer's job easier. We are doing this by offering circuits from the lab as well as evaluation board tools that allows them to just test out the ADC and then incrementally add components in the signal chain. For example, we have got an evaluation board that features a data capture card which is based on a Xilinx Virtex 4 and an ADC evaluation board.
The evaluation board features a primary path that features a passive transformer but there is also a secondary option which features an op-amp. So if they wanted to try an op-amp configuration to drive the ADC they can give it a try. Likewise on the clock we have a clock distribution chip path from our clocking products so that they can get an understanding of what a little system board looks like. We also have power LDOs and switching regulators from ADI so that they can use those rather than use a pristine power or supply source from the lab.
They can emulate a mini system or a demonstration of a signal chain. That takes them a long way in adding confidence to their design.
We also have software models from the ADC model itself. If you are running a signal chain simulation similar to Agilent's ADS or MATLAB you can download our behavior model which represents the ADC. This enables the systems engineers to look at it without even having to fire up an evaluation board.
We recognize at this level of performance there is extra care that is needed in the evaluation board and in the customer's design and we don't want them to get frustrated so we provide circuits from the lab, all the necessary apps notes and technical support.
It is a complete offering - not just the components.
EE TIMES Europe: Is the available AD9467 now?
Hall: We have been sampling customers for about two quarters. We have already sold some parts. We are targeting product release for the end of October 2010 with production quantities by November 2010.
EE TIMES Europe: So in summary what would you say are the key selling points of the new AD9467 ADC?
Hall: For engineers worldwide I think the key point is the sample rate. This translates into the bandwidth support and the AC specs which we are achieving over that bandwidth. So the catcher is 76 dBFs SNR as well as a high- to mid-90s SFDR over a wide band of signal range. They go: “Oh my Gosh you can actually get that today? That's great.”
The secondary thing is that signal bandwidth can be centered at a higher IF because that eases their design. But the first element is just the sheer resolution or the ENOBs you are getting over a bandwidth.
So it is the performance that is key and secondary points are the IF sampling and the power advantage.
Related links and articles:
250 MSPS 16-bit ADC claims new level of signal processing performance
More information about the new AD9467-250 16-bit ADC at: www.analog.com/static/imported-files/data_sheets/AD9467.pdf?ref=PR_9-20-10_AD9467 All news
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